Software-Defined Networking Architecture for NoC-based Many-Cores

Ruaro, Marcelo; Medina, Henrique; Amory, Alexandre M.; Moraes, Fernando

doi:10.1109/iscas.2018.8351830

Cited by 12 publications

(18 citation statements)

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“…The MCSoC system and hardware architecture was modeled using the Memphis MCSoC [24]. The baseline MPN, SR router design, and Controller were previously proposed in [4,5,9]. The design proposed in this work is public available at [25].…”

Section: Resultsmentioning

confidence: 99%

“…SDN is a paradigm rather than an implementation or design, which drives to different proposals. Authors [3,5,6,8,14] propose a solution based on a centralized Controller. Authors in [7,9,13] address distributed approaches, aiming to improve scalability.…”

Section: Related Workmentioning

confidence: 99%

“…Data coming from the input port is forwarded to the output with a delay of one clock cycle due to the buffering process required to avoid long wires. Further details related to the SR, the MPN, and the Controller designs are available at [4,5].…”

Section: Reference Mcsoc Architecturementioning

confidence: 99%

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A Systemic and Secure SDN Framework for NoC-Based Many-Cores

2020

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Recent exploration of Software-Defined Networking (SDN) for Many-Core Systems-on-Chip (MCSoCs) showed higher management flexibility and reduced physical complexity compared to other runtime communication management. In SDN, there is a software SDN Controller (control layer) that configures generic routers (data layer). The adoption of SDN makes the path establishment programmable and straightforward, according to different network policies, such as low power, QoS, fault-tolerance. It is also possible to change the path establishment policies at runtime without the need to redesign the NoC. Current works focus on proposing SDN architectures, lacking a systemic framework that describes the steps required to implement SDN into a Many-core environment. Security is an observed gap in SDN designs. A malicious task could configure SDN routers and take control of the NoC. The contribution of this work is to present a systemic and secure SDN framework (SDN-SS), detailing the steps required to support SDN in MCSoCs. This work also describes the iteration between the hardware, operating system, and user's tasks. The SDN-SS manages a Multiple-Physical NoC, with one packet-switching subnet and a set of circuitswitching subnets. The originality of SDN-SS includes (i) a step-by-step framework description addressing the phases required to support a secure SDN management; (ii) a secure SDN router configuration protocol; (iii) a protocol to change the subnet at runtime. Experimental results show the framework's capability to avoid DoS and Spoofing attacks while presents a low SDN router configuration overhead, corresponding up to 2% of a related work delay and a small impact over the user's task communication.

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Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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A Systemic and Secure SDN Framework for NoC-Based Many-Cores

2020

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“…Ruaro et al [ 51 ], described a layered SDNoC architecture, which uses an NoC for configuration and an SDNoC for operation. This work uses cycle-accurate RTL models and VHDL implementations to obtain performance analyzes and hardware resource estimations.…”

Section: Literature Reviewmentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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“…However, the objective of finding a general platform that suits any network for flexible chip control had a great deal in the research community. Researchers found that the concept of Software Defined Networks (SDN) can be applied to NoC [17], [18], [19], and [20]. The combination of these concepts produced a novel NoC management technology, which was called Software Defined Network on Chip (SDNoC) [21] and [22].…”

Section: Introductionmentioning

confidence: 99%

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

et al. 2021

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Photonic networks and software-defined networks are two promising technologies to improve network-onchips performance, scalability, and resource utilization. Several architectures suffer from scaling limitations, high-power consumption, and noise interference drawbacks. In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented. The proposed architecture based on a hybrid hardware-software approach, and a Software-Defined Management Orchestrator (SDMO) to separate the network control and data forwarding planes. This orchestrator has hosted on the upper hardware router as a virtual layer capable of dynamic management. It reconfigures data forwarding paths and allows dynamic execution of different algorithms in real-time, as it scales the proposed topology based on both applications and the network requirements. The proposed SD-PNoC architecture, hierarchical communication protocols, and orchestrator management policies were implemented, simulated, and tested using a customized Phoenix-SIM framework in the OMNIT++ simulation environment. Numerous simulation experiments under different conditions have been performed and have proven that the performance of the proposed architecture is better than that of the conventional electronic network on chip (ENoC). Furthermore, simulation results without using the management policies showed that the latency is reduced by 46% and 25.5% for the 4x4 and 8x8 network structures, respectively. While the power consumption is reduced by 76.5% and 78.5% for the 4x4 and 8x8 network structures, respectively. Besides, the chip area is reduced by 33.4%. Moreover, simulation results of SDMO with using the management policies for the 8x8 network structures increased the enhancement of latency from 25.5% to 37.3% and the power consumption from 78.5% to approximately 80%, which assure the ability of the proposed architecture to remarkably enhance the overall performance of complex network-on-chip structures.

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Software-Defined Networking Architecture for NoC-based Many-Cores

Cited by 12 publications

References 12 publications

A Systemic and Secure SDN Framework for NoC-Based Many-Cores

A Systemic and Secure SDN Framework for NoC-Based Many-Cores

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

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