2017
DOI: 10.1088/1748-0221/12/01/c01083
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Software and firmware co-development using high-level synthesis

Abstract: A: Accelerating trigger applications on FPGAs (using VHDL/Verilog) at the CMS experiment at CERN's Large Hadron Collider warrants consistency between each trigger firmware and its corresponding C++ model. This tedious and time consuming process of convergence is exacerbated during each upgrade study. High-level synthesis, with its promise of increased productivity and C++ design entry bridges this gap exceptionally well. This paper explores the "single source code" approach using Vivado-HLS tool for redevelopi… Show more

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Cited by 8 publications
(4 citation statements)
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“…The hardware implementations of the HL-LHC ATLAS and CMS L1T will use high-bandwidth serial I/O links for data communication and large, modern field-programmable gate arrays (FPGAs) for sophisticated and fast algorithms. The development and synthesis of FPGA firmware incorporating these algorithms is significantly enhanced in reliability, accessibility and performance with Higher Level Synthesis (HLS) tools [31]. The latest developments and expectations for future FPGAs not only include significant increases in the number of logic gates available and high-speed serial links, but also increases in the number of highbandwidth serial links per device, more sophisticated and fast DSPs, embedded Linux, and integration with high speed networking.…”
Section: Discussionmentioning
confidence: 99%
“…The hardware implementations of the HL-LHC ATLAS and CMS L1T will use high-bandwidth serial I/O links for data communication and large, modern field-programmable gate arrays (FPGAs) for sophisticated and fast algorithms. The development and synthesis of FPGA firmware incorporating these algorithms is significantly enhanced in reliability, accessibility and performance with Higher Level Synthesis (HLS) tools [31]. The latest developments and expectations for future FPGAs not only include significant increases in the number of logic gates available and high-speed serial links, but also increases in the number of highbandwidth serial links per device, more sophisticated and fast DSPs, embedded Linux, and integration with high speed networking.…”
Section: Discussionmentioning
confidence: 99%
“…The third stage is firmware design. The inputs to Xilinx Vivado are created [49,50]. The inputs are a combination of HLS and hardware description language (HDL).…”
Section: Jinst 16 P08016mentioning
confidence: 99%
“…The third stage is firmware design. The inputs to Vivado are created [46,47]. The inputs are a combination of HLS and hardware description language (HDL).…”
Section: Introductionmentioning
confidence: 99%