Softerror mitigation for multi-core processors based on thread replication

Serrano-Cases, Alejandro; Restrepo-Calle, Felipe; Cuenca-Asensi, Sergio; Martínez-Álvarez, Antonio

doi:10.1109/latw.2019.8704614

Cited by 6 publications

(7 citation statements)

References 11 publications

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“…The work in [31] analyzes the hardened-by-replication at the software level, observing that these techniques improve marginally the reliability against in-memory SEUs, but they degrade the reliability against hardware architectural faults. In [32], a software approach is adopted, in which many cores are used to launch partial replicas of the same program.…”

Section: Software Ft In Multi-threading Processorsmentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify the fault tolerance potential of interleaved-multi-threading. In this study, we apply the temporal-spatial triple modular redundancy concept to interleaved-multi-threading processors through a design solution that we call Buffered triple modular redundancy, using the soft-core Klessydra-T03 as the basis for our experiments. We then illustrate the quantitative findings of a large fault-injection simulation campaign on the fault-tolerant core and discuss the vulnerability comparison with previous representative fault-tolerant designs. The results show that the obtained resilience is comparable to a full triple modular redundancy at the cost of execution cycle count overhead instead of hardware overhead, yet with higher achievable clock frequency.INDEX TERMS Circuit faults, digital integrated circuits, fault detection, fault tolerant computing, field programmable gate arrays, microprocessors, multithreading, radiation hardening (electronics), redundancy, robustness.Open Access funding provided by 'Università degli Studi di Roma ''La Sapienza''' within the CRUI CARE Agreement

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Section: Software Ft In Multi-threading Processorsmentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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“…It is based on modular redundancy strategy and relies on the parallel execution of redundant threads on separate cores. This way it could be easily adapted to Dual or Triple Modular Redundancy depending on the number of available cores [21].…”

Section: Data Error Detectionmentioning

confidence: 99%

Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection

Pena-Fernandez

Serrano-Cases

Lindoso

et al. 2019

Microelectronics Reliability

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This work presents a new Dual-Core LockStep approach to enhance fault tolerance in microprocessors. The proposed technique is based on the combination of software-based data checking and trace-based control-flow checking through an external hardware module. The hardware module is connected to the trace interface and is able to observe the execution of all the processors in the architecture. The proposed approach has been implemented for a dual core commercial processor. Experimental results demonstrate that the proposed technique has a high error detection capability with up to 99.63% error coverage.

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“…Also, authors in [16] conclude that the usage of parallelization APIs (Application Programming Interfaces) increases the occurrence of unexpected terminations that are caught by the operating system. In this sense, recent works such as [20] and [21] have presented multi-threaded techniques in environ-ments without operating systems with promising results. In [20], authors show a multi-threaded data triplication technique that improves the fault coverage by 26× while presenting execution overheads less than 8× on average.…”

Section: Introductionmentioning

confidence: 99%

“…In [20], authors show a multi-threaded data triplication technique that improves the fault coverage by 26× while presenting execution overheads less than 8× on average. In [21], a triplication technique is evaluated showing a positive influence on the reduction of error rates.…”

Section: Introductionmentioning

confidence: 99%

“…This leads multiple instances of the same program to be run in parallel without any communication between them, excluding a little piece of code for stall and synchronization purposes. Preliminary work presented in LATS [21] evaluates the threaded TMR technique, and puts in relevance that the storage data were not protected because lifetime of several variables goes beyond the technique protection. Therefore, the present work compares the use of TMR and DWC-R techniques and also introduces the application of TMR at the storage data to improve the results of previous preliminary work.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems

Serrano-Cases¹,

Restrepo-Calle

Cuenca-Asensi³

et al. 2019

J Electron Test

Self Cite

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This article presents a software protection technique against radiation-induced faults which is based on a multi-threaded strategy. Data triplication and instructions flow duplication or triplication techniques are used to improve system reliability and thus, ensure a correct system operation. To achieve this objective, a relaxed lockstep model to synchronize the execution of both, redundant threads and variables under protection on different processing units is defined. The evaluation was performed by means of simulated fault injection campaigns in a multi-core ARM system. Results show that despite being considered techniques that imply an evident overhead in memory and instructions (Duplication With Comparison and Re-Execution -DWC-R and Triple Modular Redundancy -TMR), spreading the replicas in different instruction flows not only produce similar results than classic techniques, but also improves the computational and recovery time in presence of soft-errors. In addition, this paper highlights the importance of protecting memory-allocated data, since the instruction flow triplication is not enough to improve the overall system reliability.

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Softerror mitigation for multi-core processors based on thread replication

Cited by 6 publications

References 11 publications

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection

Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems

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