Soft error susceptibility and immune structures in dynamic random access memories (DRAMs) investigated by nuclear microprobes

Takai, M.; Kishimoto, T.; Ohno, Y.; Sayama, H.; Sonoda, K.; Satoh, S.; Nishimura, Takashi; Miyoshi, Hirokazu; Kinomura, A.; Horino, Y.; Fujii, K.

doi:10.1109/23.490913

Cited by 14 publications

(6 citation statements)

References 32 publications

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“…In this case, all strikes are basically "inside-the-well" strikes. Retrograde wells and buried layers can also be used to provide an internal electric field that opposes collection of charge deposited in the substrate [91], [92]. Even the simple use of an epitaxial substrate instead of a bulk substrate affords some level of reduced charge collection [56].…”

Section: A Technology Hardeningmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

894

427

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Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

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Section: A Technology Hardeningmentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

894

427

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“…Proposed techniques include an extra doping layer to limit substrate charge collection [8], well structures [11] to isolate the strike inside the well, and a buried layer that provides an internal electric field to oppose the deposited charge [35]. Whereas these techniques are effective in reducing SEU sensitivity, the cost from a process and materials standpoint might be excessive for mainstream applications.…”

Section: Introductionmentioning

confidence: 99%

Gate sizing to radiation harden combinational logic

Zhou

Mohanram

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

274

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Abstract-A gate-level radiation hardening technique for costeffective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve costeffective tradeoffs between overhead and soft error failure rate reduction. The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure rate for specified overhead costs (area, power, and delay). Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate. A full set of experimental results for process technologies ranging from 180 to 70 nm demonstrates the cost-effective tradeoffs that can be achieved. On average, the proposed technique has a radiation hardening overhead of 38.3%, 27.1%, and 3.8% in area, power, and delay for worst case SEUs across the four process technologies.

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“…The charge collection from the substrate is reduced, but not fully avoided, rising the dopant concentration in a p-well deep in the substrate [10], hence it is not completely unexpected that very high charge deposition close to the p þ implant modifies locally its behavior, reducing its effectiveness. In Fig.…”

Section: Beam Testsmentioning

confidence: 99%