Soft-Error-Immune Read-Stability-Improved SRAM for Multi-Node Upset Tolerance in Space Applications

Pal, Soumitra; Mohapatra, Sayonee; Ki, Wing-Hung; Islam, Aminul

doi:10.1109/tcsi.2021.3085516

Cited by 23 publications

(17 citation statements)

References 29 publications

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“…T RA (read access time or read delay) is estimated from the time the wordline crosses 50% of its full swing to the time that one of the bitlines (BL/BLB) is discharged by 50 mV from its initial high level. 3,6,21,22 The value of the bitline capacitance and the amount of read current through the access transistor are the major factors which impact the T RA . All the 10T comparison cells and RHD12T have only one identically sized NMOS access transistor connected to each bitline.…”

Section: Read Delay Comparisonmentioning

confidence: 99%

“…Recent studies have mentioned that write ability can be estimated more reliably using the wordline write trip voltage (WWTV). 1,3,6,27 The WWTV is estimated as the potential difference between V DD and the WL voltage when the voltages at storage nodes Q and QB flip. 1,3,6 The WWTV justification is similar to that for the T WA .…”

Section: Write Delay and Write Ability Comparisonmentioning

confidence: 99%

“…1,3,6,27 The WWTV is estimated as the potential difference between V DD and the WL voltage when the voltages at storage nodes Q and QB flip. 1,3,6 The WWTV justification is similar to that for the T WA . That means, if a cell takes a longer time to flip the stored data, it shows a lower WWTV.…”

Section: Write Delay and Write Ability Comparisonmentioning

confidence: 99%

“…The ability of the proposed RHRD12T cell to function reliably in advanced technology nodes is verified by estimating various important design metrics with the 16-nm predictive technology model (PTM). The chosen method to verify the scalability of RHRD12T is the same as that mentioned in Pal et al 3,6 and Pal and Islam. 30 For analysis and comparison, the simulation results of RHRD12T are compared with those of RHD12T in 16-nm PTM technology.…”

Section: Scalabilitymentioning

confidence: 99%

“…Though softerror does not damage the electronic device permanently, it does result in system malfunction. 2,6 Researchers have proposed various soft-error mitigation techniques such as error correction codes (ECCs) and radiation-hardened circuits. However, ECCs have power, delay, and area overhead.…”

mentioning

confidence: 99%

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Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

Circuit Theory & Apps

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In advanced technology, static random-access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high-energy particle strikes, which cause soft-error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation-hardened readdecoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read-decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02Â/1.06Â/1.07Â/1.08Â over NS10T/RHD12T/PS10T/RHBD10T at V DD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single-event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. K E Y W O R D Sdigital circuit, low power design, memory design, read stability, SRAM | INTRODUCTIONSatellites have become an integral part of human society, as we rely on satellite communication for a wide range of services, from meteorology to disaster monitoring, from navigation systems to military operations, and so on. 1 As the technology is advancing, lightweight satellites are replacing heavyweight satellites because of their higher manufacturing cost. 2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase. To withstand this harsh environment, special electronic components and circuits are used. Once a radiation particle strikes a logic circuit at its sensitive node, it generates electron-hole pairs (Figure 1A). These pairs become separated and accumulate at the sensitive node. 3 The accumulated charge at the sensitive node then generates a transient voltage pulse. If enough charge (i.e., critical charge, Q C ) is

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Section: Read Delay Comparisonmentioning

confidence: 99%

Section: Write Delay and Write Ability Comparisonmentioning

confidence: 99%

Section: Write Delay and Write Ability Comparisonmentioning

confidence: 99%

Section: Scalabilitymentioning

confidence: 99%

mentioning

confidence: 99%

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Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

Circuit Theory & Apps

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A review on radiation‐hardened memory cells for space and terrestrial applications

Mukku¹,

Lorenzo²

2022

Circuit Theory & Apps

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Over the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area.Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resilience techniques and methods to mitigate this upset mess. In addition, we also investigated the importance of Q Crit and the impact of Q Crit on device scaling parameters in upset mechanism, probability of memory failure, and the figure of metrics for the stability of memory cells.critical charge, figure of metric, single event upset, single event multiple node upset, soft error | INTRODUCTIONTo enhance the functionality of system-on-chip (SoC), designers scale down the dimensions of the transistors. 1 According to the international technology roadmap for semiconductors (ITRS) prediction on memory size, and its processing engines on mobile type SoC, it is expected to rise by a factor of 18 between 2013 and 2025, 2,3 which is shown in Figure 1. Massive increasing the transistor count certainly increases the power consumption and degrade the mobile battery's life.Recent SoCs are embedded with static random access memory (SRAM) memories due to the faster and more reliable read/write approaches. Therefore, these SRAMs are used as cache and main memories. Moreover, SRAM memories occupy a maximum area on SoC's. 2 Hence, chip designers scale down the process technology of the memories. The problem with process technology scaling would lower the standard operating voltage, conversely, due to the process variations, memory density increases. 4 Figure 2 shows the trends of industrial standard processors and SRAM memories with various operating voltages at different technology nodes presented in ISSCC. 3 Scaling the process technology node of SRAM memories is more sensitive to transistor variations. 5 This scaling also increases the soft error rate (SER). Ibe et al 6 discuss the SER of SRAM memories in 22 nm node rises by a factor of 7 as compared with 130 nm design. On the other hand, when an electronic component is subjected to radiation, its electrical properties change due to technology node scaling, large densities, and lower operating voltages. These exposures to radiation cause temporary or permanent system breakdown.Three distinct radiation environments are feasible to define, from earth's sea level to the planet's space orbit. They are terrestrial, atmospheric, and van Allen belt radiations. The National Aeronautical Space Administration (NASA) investigated spacecraft anomalies between 1974 and 1994 space missions. 7 Among those 100 various missions, it is clear that 35% and above of anomalies are caused to spacecraft failure due to the electronic component's radiation effects. So

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Circuit-level technique to design robust SRAM cell against radiation strike

Pandey,

Islam

2023

Microsyst Technol

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Soft-Error-Immune Read-Stability-Improved SRAM for Multi-Node Upset Tolerance in Space Applications

Cited by 23 publications

References 29 publications

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

A review on radiation‐hardened memory cells for space and terrestrial applications

Circuit-level technique to design robust SRAM cell against radiation strike

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