Soft Error Detection through Low-level Re-execution

Abstract

Nowadays, embedded systems are widely used both in general-purpose as well as in safety-critical applications. Due to technological advances, these embedded systems can operate on extremely small footprints and low voltages. This, however, makes them more susceptible to external disturbances such as electromagnetic interference. These disturbances can cause single event upsets, a bit being flipped inside the microcontroller, which in turn can result in unexpected and unpredictable behavior of the system due to control flow errors or data flow errors. Many software-implemented control flow and data flow error detection techniques have been examined in the past. However, these techniques often require a large amount of devoted CPU registers to work correctly. Not every system is able to devote a large portion of its registers to an error detection technique. This paper proposes DETECTOR: a new low-level re-execution based technique protecting against both data flow and control flow errors, while using only three CPU registers. The experimental results presented in this paper are promising, showing that DETECTOR is able to significantly increase the reliability of the system.

Utilizing Parity Checking to Optimize Soft Error Detection Through Low-Level Reexecution

“…This causes a checkpoint to be inserted in the hot loop, thus, introducing many memory access instructions into the program. To show the impact of DETECTOR, the ARMv7-M instruction set architecture (ISA) is used to count the added instruction cycles since this ISA was used in the publication where DETECTOR was presented [18].…”

“…They have been chosen based on their different internal structures and complexity. As a reference, the case studies were also compiled without an error detection technique and with five state-of-the-art error detection techniques: SWIFT [21], FDSC [16], CFCSS [19], RACFED [20], and DETECTOR [18]. The 32-bit ARMv7-M driven Cortex-M3 processor was used as the target device, for it is an industry-leading embedded processor used in many application domains [22].…”

“…Although effective, the reduced register availability can cause a compilation failure when the compiler cannot find enough registers to compile the program. To address this shortcoming, we previously presented Soft Error Detection through Low-level Re-execution (DETECTOR), which only uses three CPU registers by relying on a re-execution-based algorithm [18].…”

Impact of Selective Implementation on Soft Error Detection Through Low-level Re-execution

“…This requires a lot of instructions, including again memory operations, further increasing the ETO. These factors combined, make that the execution time overhead ranges from 2.09 up to 11.95, depending on the case study on which the technique was applied [11].…”

“…This can cause the register allocation process of the compilation process to fail for more advanced and industrial grade programs. To address this issue, we recently developed a novel software-implemented low-level technique, called DETECTOR [11]. DETECTOR uses only three CPU registers, while effectively providing protection against both CFEs and DFEs.…”