Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis

Cuppini, Matteo; Mucci, Claudio; Scarselli, Eleonora Franchi

doi:10.1109/tvlsi.2014.2384740

Cited by 8 publications

(16 citation statements)

References 18 publications

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“…One also finds synthesizable eFPGAs with a datapath-oriented structure [35]. Our proposed eFPGA is fully-synthesizable -soft IP as reported in Table I -as shown in [25] and the interconnection network is based on a multi-stage switching network [36]. This type of interconnection network allows full-routability and provides sustainable area overhead in small-size devices.…”

Section: Embedded Fpgasmentioning

confidence: 99%

“…In this section we describe our proposed system architecture. We propose a digital circuit, as introduced in [13], which consists of a PULPino microcontroller [15] coupled with an embedded FPGA template [25] [38]. The interfacing is done through an AMBA Advanced Peripheral Bus (APB) as shown in Fig.…”

Section: System-level Architecturementioning

confidence: 99%

“…2) eFPGA Software Tools: A complete CAD flow for the proposed eFPGA was implemented as explained in [25]. The flow starts with an HDL code technology independent presynthesis in logic operators and flip-flop functionalities using Synopsys Design Compiler [39].…”

Section: B Embedded Fpga Sub-systemmentioning

confidence: 99%

See 2 more Smart Citations

A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

Renzini

Mucci

Rossi

et al. 2020

IEEE Trans. Circuits Syst. I

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This paper proposes a reconfigurable System-on-Chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at a lower power consumption and higher responsiveness than with processor-based execution. To the best of the authors' knowledge this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating Bipolar, CMOS and DMOS devices, typically featuring a small amount of metal layers when compared to traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable, since the eFPGA is based on a soft-core approach. The paper presents the results of integrating an eFPGA with a computational capability of 1k equivalent gates in STMicroelectronics 90 nm BCD technology featuring five metal layers and high-k transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20-27% area overhead, but has a straightforward benefit in terms of energy consumption which proves reduced from about 10× to 800×. In terms of latency, the eFPGA implementation allows a gain from 8× to 145× comparing the pure cycles count.

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Section: Embedded Fpgasmentioning

confidence: 99%

Section: System-level Architecturementioning

confidence: 99%

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A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

Renzini

Mucci

Rossi

et al. 2020

IEEE Trans. Circuits Syst. I

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“…The digital system is composed of the open-source ultralowpower microcontroller PULPino [7] coupled with our softcore eFPGA [6]. Interfacing is done through AMBA Advanced Peripheral Bus (APB) as shown in Fig.…”

Section: System-level Architecturementioning

confidence: 99%

“…The introduction of reconfigurable SoCs in the Smart-Power arena is a new challenge for the technologies driving this area, due to the peculiarity of both system and technology. In this context, we present an energy-aware analysis of a Smart-Power SoC integrating a soft-core eFPGA architecture [6] tailored to small-computational tasks within the open-source PULPino microcontroller system [7] on STMicroelectronics 0.13 µm BCD technology.…”

Section: Introductionmentioning

confidence: 99%

A Fully Programmable eFPGA-Augmented SoC for Smart-Power Applications

Renzini

Rossi

Scarselli

et al. 2018

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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This paper proposes a reconfigurable System-on-Chip (SoC) for Smart-Power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications, featuring digital elaboration with small computational load, at a lower power consumption and higher responsiveness compared to processor-based implementation. Added value of the proposed system is that the whole digital system is synthesizable, since also the eFPGA is based on a soft-core approach. In the paper we discuss the application domain and present the results of integrating an eFPGA with a computational capability of ≈1K equivalent gates in the STMicroelectronics 0.13 µm Bipolar, CMOS, DMOS (BCD) Smart-Power technology featuring only four metal layers. As expected, eFPGA integration in the SoCs introduces a significant area-overhead (about 20÷25%), but has a straightforward benefit in terms of energy consumption reduction compared to processorbased implementations. On average, based on our analysis, the energy gain achievable in this scenario can be quantified in a couple of orders of magnitude.

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Research and Design of FPGA Embedded System

Jiang

2020

Advances in Intelligent Systems and Computing

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Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis

Cited by 8 publications

References 18 publications

A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

A Fully Programmable eFPGA-Augmented SoC for Smart-Power Applications

Research and Design of FPGA Embedded System

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