SoC Memory System Design

High definition (HD) video decoder processes a great amount of data within a bounded time and thus requires high memory bandwidth. The memory bandwidth will dominate system performance, especially in embedded systems. In this paper, we propose a lossless hybrid display frame compression algorithm called HPE (Hybrid Pixel Encoding) for HD video decoder considering high compression performance and real time operation. The algorithm combines dictionary coding and run length coding to achieve a low compression ratio. We integrate the proposed design into an H.264 decoder. Experimental results show that the proposed algorithm gains 67.7% of data reduction ratio on average when decoding 1080-HD video. It is much more effective than all previous works.

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“…We utilize data reduction ratio (DRR) to judge the efficiency of the display frame compression algorithms. The definition of DRR is shown in (2).…”

Section: A Methodologymentioning

confidence: 99%

“…Off-chip memory access is not only a major bottleneck in system performance [1], [2] but also an important source of power consumption. We have previously proposed a fully hardwired H.264 HD video decoder (HDV) in a high performance multimedia SoC to decode full HD video at 30 frames per second.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Pixel Encoding: An Effective Display Frame Compression Algorithm for HD Video Decoder

Li¹,

Wang

Zhang³

2012

2012 IEEE 15th International Conference on Computational Science and Engineering

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“…It is based on the fact that in most SoCs the biggest share of power is consumed in only a few components, such as caches and big on-chip memories [2]. Therefore, the total number of events to consider for power estimation can be drastically reduced.…”

Section: Introductionmentioning

confidence: 99%

A lightweight-system-level power and area estimation methodology for application specific instruction set processors

Shah

Wagner

Schuster

et al. 2014

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Detailed power estimation is a tedious and time consuming task in modern ASIP design. To facilitate this process, we present faster and fully automated estimation models for use at system level. In the first step of our approach, we calculate normalized values for all the basic design components of the processor that are related to power and area (e.g. memories, register files, function units, etc). These normalized values are estimated based on processors with different configurations (e.g., different memory sizes) and then stored in a database. Later, in the second step, this information is used to estimate the power of new derived architectures. To that end, we combine the previously calculated normalized power data with the component configurations and switching information from system-level simulation. The approach is demonstrated on the example of an Intel ASIP design flow (Silicon Hive). We report power and area estimates for four different ASIP designs. The mean error of the area prediction is 10%, while the mean error in power prediction is 15%.

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“…Off-chip memory access is not only a major bottleneck in system performance [2], [3] but also an important source of power consumption. Many studies [4]- [7] target on decreasing the clock cycles of DRAM penalty to reduce memory traffic.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Pixel Encoding: An Effective Algorithm for Frame Buffer Compression

Li¹,

Jiang²,

Meng³

2012

2012 IEEE 12th International Conference on Computer and Information Technology

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Display controller processes a great amount of data within a bounded time and thus requires high memory bandwidth. The memory bandwidth will dominate system performance, especially in embedded systems. In this paper, we propose a hybrid algorithm called APE (Adaptive Pixel Encoding) for lossless frame buffer compression considering high compression performance and real time operation. The algorithm combines dictionary coding and run length coding to achieve a low compression ratio. We integrate APE frame buffer compression architecture into a display controller. Experimental results show that the proposed algorithm gains 19.7% of compression ratio and 66.2% of memory bandwidth reduction ratio during sweep operation. It is much more effective than all previous works.

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SoC Memory System Design

Cited by 6 publications

References 48 publications

Hybrid Pixel Encoding: An Effective Display Frame Compression Algorithm for HD Video Decoder

Hybrid Pixel Encoding: An Effective Display Frame Compression Algorithm for HD Video Decoder

A lightweight-system-level power and area estimation methodology for application specific instruction set processors

Adaptive Pixel Encoding: An Effective Algorithm for Frame Buffer Compression

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