SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications

Ni, Kai; Smith, J. A.; Grisafe, Benjamin; Rakshit, Titash; Obradovic, B.; Kittl, Jorge; Rödder, M.; Datta, Suman

doi:10.1109/iedm.2018.8614496

Cited by 103 publications

(51 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table 2 shows a comparative study between FeFET-based analog synapse and various other candidates like PCM (Burr et al, 2010;Athmanathan et al, 2016;Ambrogio et al, 2018) and RRAM (Lee et al, 2012;Wu et al, 2017;Wu W. et al, 2018;Luo et al, 2019). One major benefit of using FeFET for implementing analog synapse is the reduced variability to less that 0.5% (Luo et al, 2019) and an order of magnitude reduction in write energy (Dünkel et al, 2018;Ni et al, 2019b). The cell area is comparable to that of PCM and RRAM.…”

Section: Discussionmentioning

confidence: 99%

“…The FeFET-based analog synapse is realized using voltage-dependent partial polarization switching in multi-domain ferroelectric thin film ( Jerry et al, 2018a , b ). Recent experimental works have shown the ability to program FeFETs with voltage pulse widths as low as 50 ns ( Jerry et al, 2018b ) while the programming voltage can be brought down from 4 to 1.8 V by engineering the gate stack by adding an additional metal layer between the ferroelectric capacitor and MOS capacitor ( Ni et al, 2019b ). Table 2 shows a comparative study between FeFET-based analog synapse and various other candidates like PCM ( Burr et al, 2010 ; Athmanathan et al, 2016 ; Ambrogio et al, 2018 ) and RRAM ( Lee et al, 2012 ; Wu et al, 2017 ; Wu W. et al, 2018 ; Luo et al, 2019 ).…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

et al. 2020

View full text Add to dashboard Cite

The two possible pathways toward artificial intelligence (AI)-(i) neuroscience-oriented neuromorphic computing [like spiking neural network (SNN)] and (ii) computer science driven machine learning (like deep learning) differ widely in their fundamental formalism and coding schemes (Pei et al., 2019). Deviating from traditional deep learning approach of relying on neuronal models with static nonlinearities, SNNs attempt to capture brainlike features like computation using spikes. This holds the promise of improving the energy efficiency of the computing platforms. In order to achieve a much higher areal and energy efficiency compared to today's hardware implementation of SNN, we need to go beyond the traditional route of relying on CMOS-based digital or mixed-signal neuronal circuits and segregation of computation and memory under the von Neumann architecture. Recently, ferroelectric field-effect transistors (FeFETs) are being explored as a promising alternative for building neuromorphic hardware by utilizing their nonvolatile nature and rich polarization switching dynamics. In this work, we propose an all FeFET-based SNN hardware that allows low-power spike-based information processing and co-localized memory and computing (a.k.a. in-memory computing). We experimentally demonstrate the essential neuronal and synaptic dynamics in a 28 nm high-K metal gate FeFET technology. Furthermore, drawing inspiration from the traditional machine learning approach of optimizing a cost function to adjust the synaptic weights, we implement a surrogate gradient (SG) learning algorithm on our SNN platform that allows us to perform supervised learning on MNIST dataset. As such, we provide a pathway toward building energy-efficient neuromorphic hardware that can support traditional machine learning algorithms. Finally, we undertake synergistic device-algorithm co-design by accounting for the impacts of device-level variation (stochasticity) and limited bit precision of on-chip synaptic weights (available analog states) on the classification accuracy.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

et al. 2020

View full text Add to dashboard Cite

show abstract

“…Recently, programming voltage as low as 1.8 V has been experimentally demonstrated for FeFET by engineering the device structure and by adding a middle metal layer between the ferroelectric capacitor and MOS capacitor [25]. Therefore, I/O transistors at the 32-nm node can be applied to support the 1.8-V programming voltage.…”

Section: Prospect Of Scalingmentioning

confidence: 99%

Benchmark of Ferroelectric Transistor-Based Hybrid Precision Synapse for Neural Network Accelerator

Luo

Wang

Peng

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

View full text Add to dashboard Cite

In-memory computing with analog nonvolatile memories can accelerate the in situ training of deep neural networks. Recently, we proposed a synaptic cell of a ferroelectric transistor (FeFET) with two CMOS transistors (2T1F) that exploit the hybrid precision for training and inference, which overcomes the challenges of nonlinear and asymmetric weight update and achieves nearly software comparable training accuracy at the algorithm level. In this paper, we further present the circuit-level benchmark results of this hybrid precision synapse in terms of area, latency, and energy. The corresponding array architecture is presented and the array-level operations are illustrated. The benchmark is conducted by multilayer-perceptron (MLP) + NeuroSim framework with comparison to other capacitor-assisted (e.g., 3T1C + 2PCM) hybrid precision cell. The design tradeoffs and scalability are discussed between different implementations.

show abstract

“…The growth of epitaxial thin films allowed the demonstration of ferroelectric memristors [1], however, integrating such films on CMOS remains challenging and expensive, requiring flip-chip or wafer bonding techniques. The discovery of ferroelectricity in hafnium oxide enabled the demonstration of ferroelectric memristors in the Front-and Back-End-Of-Line (BEOL) [2], [3] through techniques allowing crystallization in the ferroelectric phase with a low thermal budget [4]. Ferroelectric Tunnel Junctions (FTJs) possess only two terminals and are a desirable approach for crossbar array fabrication.…”

Section: Introductionmentioning

confidence: 99%

A BEOL Compatible, 2-Terminals, Ferroelectric Analog Non-Volatile Memory

Bégon‐Lours

Halter

Pineda

et al. 2021

2021 5th IEEE Electron Devices Technology &Amp; Manufacturing Conference (EDTM)

View full text Add to dashboard Cite

A Ferroelectric Analog Non-Volatile Memory based on a WOx electrode and ferroelectric HfZrO4 layer is fabricated at a low thermal budget (~375˚C), enabling BEOL processes and CMOS integration. The devices show suitable properties for integration in crossbar arrays and neural network inference: analog potentiation/depression with constant field or constant pulse width schemes, cycle to cycle and device to device variation <10%, ON/OFF ratio up to 10 and good linearity. The physical mechanisms behind the resistive switching and conduction mechanisms are discussed.

show abstract

SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications

Cited by 103 publications

References 5 publications

Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

Benchmark of Ferroelectric Transistor-Based Hybrid Precision Synapse for Neural Network Accelerator

A BEOL Compatible, 2-Terminals, Ferroelectric Analog Non-Volatile Memory

Contact Info

Product

Resources

About