Abstract:In this paper, the design of a dual-mode transceiver for a power-line telecommunications (D-PLT) is described. We investigate on designing a system architecture of the D-PLT, adopting an efficient modulation technique against power-line channel and supporting a high reliability, which is well suited for the CENELEC B, C, and D bands roughly from 90 to 150 kHz. The proposed D-PLT is eventually integrated to a system-on-achip (SoC), synthesizing all of a baseband transceiver, a channel forward error correction (… Show more
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