2021
DOI: 10.48550/arxiv.2104.09768
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SME: A High Productivity FPGA Tool for Software Programmers

Carl-Johannes Johnsen,
Alberte Thegler,
Kenneth Skovhede
et al.

Abstract: For several decades, the CPU has been the standard model to use in the majority of computing. While the CPU does excel in some areas, heterogeneous computing, such as reconfigurable hardware, is showing increasing potential in areas like parallelization, performance, and power usage. This is especially prominent in problems favoring deep pipelining or tight latency requirements. However, due to the nature of these problems, they can be hard to program, at least for software developers. Synchronous Message Exch… Show more

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Cited by 1 publication
(2 citation statements)
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“…In this paper, we explore a high-level approach for implementing Convolutional Neural Network (CNN) (a special type of NN) on FPGAs; namely Synchronous Message Exchange (SME) [4,5,11,17,18,21,22]. Being a high-level FPGA programming model, it is only natural to compare our implementation to the most widespread high-level FPGA programming model: High-Level Synthesis (HLS) [2].…”
Section: Contributionmentioning
confidence: 99%
See 1 more Smart Citation
“…In this paper, we explore a high-level approach for implementing Convolutional Neural Network (CNN) (a special type of NN) on FPGAs; namely Synchronous Message Exchange (SME) [4,5,11,17,18,21,22]. Being a high-level FPGA programming model, it is only natural to compare our implementation to the most widespread high-level FPGA programming model: High-Level Synthesis (HLS) [2].…”
Section: Contributionmentioning
confidence: 99%
“…Various tools address the issue of FPGA HDL code generation. This paper examines High-Level Synthesis (HLS) [2] and Synchronous Message Exchange (SME) [11] approaches, spanning high and low levels respectively. While other tools exist, some even beyond the span of HLS and SME, they will not be covered in this paper.…”
Section: Programming Fpgasmentioning
confidence: 99%