2020
DOI: 10.1109/tia.2020.2980729
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Small-Signal Disturbance Compensation Control for LCL-Type Grid-Connected Converter in Weak Grid

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Cited by 41 publications
(20 citation statements)
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“…where U is the inverter output voltage, R and L are the resistance and inductance of the grid side. Through (29), (31), where pk K and ik K are the first and second resonance coefficients, and the relationship between them is pk = ik K K R L [20] . c  is the bandwidth parameter, and the general value range is 5~15rad/s.…”
Section: Control Systemmentioning
confidence: 99%
See 1 more Smart Citation
“…where U is the inverter output voltage, R and L are the resistance and inductance of the grid side. Through (29), (31), where pk K and ik K are the first and second resonance coefficients, and the relationship between them is pk = ik K K R L [20] . c  is the bandwidth parameter, and the general value range is 5~15rad/s.…”
Section: Control Systemmentioning
confidence: 99%
“…The main factors affecting the transient response capability of the inverter are the digital delay process, the control parameter design of the current loop, and the phase lock speed of the PLL. [20] optimizes the current loop parameters through a multi-objective function to improve the transient response capability of the inverter, a simple small signal supplementary control is proposed.…”
Section: Introductionmentioning
confidence: 99%
“…However, the PLL-based synchronization strategy may suffer from stability issues, especially when the VSC is connected to a weak grid [9], [10]. To address the instability issue induced by the PLLs, one solution is to introduce extra feedforward or feedback terms in the current control loop, such as the output impedance reshaping method [11] and small-signal disturbance compensation control [12]. However, these solutions increase the implementation complexity of the current control loop and are dependent on the operating point of the system.…”
Section: Introductionmentioning
confidence: 99%
“…However, this method often results in a PLL with a very slow dynamic response which is not desirable (see e.g., [5], [32], [33]). Modifying the structure of the outer control loops, the AVC and PLL, by adding linear functions of output voltage and currents has been proposed to improve the VSC-WG stability [15], [26], [32], [34]. Essentially, these methods change the output impedance of the VSC such that the sourceload admittance matching holds between the VSC and WG.…”
Section: Introductionmentioning
confidence: 99%