2018 IEEE International Symposium on Circuits and Systems (ISCAS) 2018
DOI: 10.1109/iscas.2018.8351645
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Small Area and Low Power Hybrid CMOS-Memristor Based FIFO for NoC

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Cited by 2 publications
(1 citation statement)
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“…Their power modeling and comparison of different routing algorithms showed more buffer depth more power drawn, more virtual channels more rapidly energy increases, more adaptive algorithm more power it consumes than deterministic ones. A new and hybrid first in first out (FIFO) architecture for reducing power in NoCs was introduced in [46]. Here the authors used a Complementary metal oxide semiconductor (CMOS) Memristor in FIFO which is a non-volatile, scalable and area efficient device.…”
Section: 32mentioning
confidence: 99%
“…Their power modeling and comparison of different routing algorithms showed more buffer depth more power drawn, more virtual channels more rapidly energy increases, more adaptive algorithm more power it consumes than deterministic ones. A new and hybrid first in first out (FIFO) architecture for reducing power in NoCs was introduced in [46]. Here the authors used a Complementary metal oxide semiconductor (CMOS) Memristor in FIFO which is a non-volatile, scalable and area efficient device.…”
Section: 32mentioning
confidence: 99%