2004
DOI: 10.1145/1013886.1007541
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Slicing tools for synchronous reactive programs

Abstract: In this paper, we present two slicing tools: VHDL Slice and Est slice that compute static executable slices of VHDL and Esterel programs respectively. The slicers have been tested on a number of small and medium sized examples.

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Cited by 3 publications
(4 citation statements)
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“…Because previous works [12]- [14] focus on correct and complete representations, they are not proper for practical analyzers based on flow analyses of existing imperative languages.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…Because previous works [12]- [14] focus on correct and complete representations, they are not proper for practical analyzers based on flow analyses of existing imperative languages.…”
Section: Resultsmentioning
confidence: 99%
“…Flow information is a basis of most program analyses, and some analyzers [12]- [14] have their own structures for flow information.…”
Section: Related Workmentioning
confidence: 99%
“…Ramesh et al [26] present two static backward slicing algorithms that compute slices of Esterel programs (FSM language) and VHDL programs used for developing synchronous reactive systems. The slicing criterion is an event or a set of events.…”
Section: Related Workmentioning
confidence: 99%
“…We have described a simulator and model checker for our distributed reactive systems model in [14,15]. We have added an abstraction-refinement algorithm to the tool based on the ideas in this paper.…”
Section: Experiencementioning
confidence: 99%