Slice-balancing H.264 video encoding for improved scalability of multicore decoding

Roitzsch, Michael

doi:10.1145/1289927.1289969

Cited by 46 publications

(26 citation statements)

References 6 publications

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“…Decoding using slice-level parallelism has been presented in [17]. The idea of the work was based on applying decoding time prediction at the encoder stage.…”

Section: Slice-levelmentioning

confidence: 99%

“…The only drawbacks associated with this level are the increasing bit rate and degradation of visual quality when the number of slices increases [13]. Fourthly, MB-level and block-level coding incur no bit rate degradation; nevertheless, both are associated with high synchronization costs because of the small-sized parallel unit, dependency among them [17], and poor scalability [5], which render them incompatible with the current trend of multicore. Given this remarks, parallel granularity in video coding could potentially reflect the performance of a parallel system in terms of scalability, synchronization cost, and memory requirements.…”

Section: Comparison Of the H264 Data-level Parallelismsmentioning

confidence: 99%

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Data-Level Parallel Approaches for the H.264/AVC: A Review from the Encoder and the Decoder Perspectives

Aboalmaaly¹

2017

ijecs

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Abstract:In order to enable easier transmission and storage of videos, video-coding techniques are used as data compression process that is intended to reduce the size of raw video without sacrificing its visual quality. The H.264 is relatively one of the recent video compression standards, which has proved to outperform former standards in terms of compression efficiency. However, it's associated with mush higher computational complexity. Several software-based as well as hardware-based approaches have been suggested to tackle this problem by using several flavours of data-level parallel approaches for the encoder and decoder sides. In this paper, these approaches are presented and compared in form of a comparative review. The suitability of one particular approach is determined based to the architecture used.

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“…Decoding using slice-level parallelism has been presented in [17]. The idea of the work was based on applying decoding time prediction at the encoder stage.…”

Section: Slice-levelmentioning

confidence: 99%

Section: Comparison Of the H264 Data-level Parallelismsmentioning

confidence: 99%

Data-Level Parallel Approaches for the H.264/AVC: A Review from the Encoder and the Decoder Perspectives

Aboalmaaly¹

2017

ijecs

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“…Roitzsch [26] proposed a slice-balancing approach to improve the load balance of exploiting slice-level parallelism. MB-level parallelism has been presented in theoretical and simulation analysis as scalable and efficient.…”

Section: Problem Of Choosing Data Sizementioning

confidence: 99%

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the largest challenges for coarse-grained reconfigurable arrays (CGRAs) is how to efficiently map applications. The key issues for mapping are (1) how to reduce the memory bandwidth, (2) how to exploit parallelism in algorithms and (3) how to achieve load balancing and take full advantage of the hardware potential. In this paper, we propose a novel parallelism scheme, called 'Hybrid partitioning', for mapping a H.264 high definition (HD) decoder onto REMUS-II, a CGRA systemon-chip (SoC). Combining good features of data partitioning and task partitioning, our methodology mainly consists of three levels from top to bottom: (1) hybrid task pipeline based on slice and macroblock (MB) level; (2) MB row-level data parallelism; (3) sub-MB level parallelism method. Further, on the sub-MB level, we propose a few mapping strategies such as hybrid variable block size motion compensation (Hybrid VBSMC) for MC, 2D-wave for intra 4 × 4, parallel processing order for deblocking. With our mapping strategies, we improved the algorithm's performance on REMUS-II. For example, with a luma 16 × 16 MB, the Hybrid VBSMC achieves 4 times greater performance than VBSMC and 2.2 times greater performance than fixed 4 × 4 partition approach. Finally, we achieve 1080p@33fps H.264 high-profile (HiP)@level 4.1 decoding when the working frequency of REMUS-II is 200 MHz. Compared with typical hardware platforms, we can achieve better performance, area, and flexibility. For example, our performance achieves approximately 175% improvement than that of a commercial CGRA processor XPP-III while only using 70% of its area.

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“…Chen et al [7] proposed a combination of frame-and slice-level parallelism. Roitzsch [16] proposed a scheme based on slice- level parallelism by modifying the encoder. Baik et al [4] have implemented a parallel version of H.264 on the Cell processor.…”

Section: Parallelization Opportunitiesmentioning

confidence: 99%

Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine

Ching

Juurlink

Meenderinck

2010

Proceedings of the 24th ACM International Conference on Supercomputing

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How to develop efficient and scalable parallel applications is the key challenge for emerging many-core architectures. We investigate this question by implementing and comparing two parallel H.264 decoders on the Cell architecture. It is expected that future many-cores will use a Cell-like local store memory hierarchy, rather than a non-scalable shared memory. The two implemented parallel algorithms, the Task Pool (TP) and the novel Ring-Line (RL) approach, both exploit macroblock-level parallelism. The TP implementation follows the master-slave paradigm and is very dynamic so that in theory perfect load balancing can be achieved. The RL approach is distributed and more predictable in the sense that the mapping of macroblocks to processing elements is fixed. This allows to better exploit data locality, to overlap communication with computation, and to reduce communication and synchronization overhead. While TP is more scalable in theory, the actual scalability favors RL. Using 16 SPEs, RL obtains a scalability of 12x, while TP achieves only 10.3x. More importantly, the absolute performance of RL is much higher. Using 16 SPEs, RL achieves a throughput of 139.6 frames per second (fps) while TP achieves only 76.6 fps. A large part of the additional performance advantage is due to hiding the memory latency. From the results we conclude that in order to fully leverage the performance of future many-cores, a centralized master should be avoided and the mapping of tasks to cores should be predictable in order to be able to hide the memory latency.

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Slice-balancing H.264 video encoding for improved scalability of multicore decoding

Cited by 46 publications

References 6 publications

Data-Level Parallel Approaches for the H.264/AVC: A Review from the Encoder and the Decoder Perspectives

Data-Level Parallel Approaches for the H.264/AVC: A Review from the Encoder and the Decoder Perspectives

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine

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