SleepWalker: A 25-MHz 0.4-V Sub-$\hbox{mm}^{2}$ 7-$\mu\hbox{W/MHz}$ Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes

Bol, David; Vos, Julien De; Hocquet, Cédric; Botman, François; Durvaux, François; Boyd, Sarah; Flandre, Denis; Legat, Jean-Didier

doi:10.1109/jssc.2012.2218067

Cited by 121 publications

(55 citation statements)

References 27 publications

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“…Only the transistors on slower timing arcs are allowed to be upsized, the ones on faster timing arcs are down sized to save area. In [12], a standard cell library in 65 nm is presented, where by upsizing the channel length of all transistors in a given cell, the energy per operation value is reduced by about 15%. In this paper, the standard cells are tuned individually, with various length and width selections to have balanced transition currents.…”

Section: Sub-threshold Cell Sizing Methodologymentioning

confidence: 99%

Sub-Threshold Standard Cell Sizing Methodology and Library Comparison

Liu

Gyvez

Ashouei

2013

JLPEA

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Abstract:Scaling the voltage to the sub-threshold region is a convincing technique to achieve low power in digital circuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold sizing methodology of [1,2] on 40 nm and 90 nm standard cell libraries. The concept of the proposed sizing methodology consists of balancing the mean of the sub-threshold current of the equivalent N and P networks. In this paper, the equivalent N and P networks are derived based on the best and worst case transition times. The slack available in the best-case timing arc is reduced by using smaller transistors on that path, while the timing of the worst-case timing arc is improved by using bigger transistors. The optimization is done such that the overall area remains constant with regard to the area before optimization. Two sizing styles are applied, one is based on both transistor width and length tuning, and the other one is based on width tuning only. Compared to super-threshold libraries, at 0.3 V, the proposed libraries achieve 49% and 89% average cell timing improvement and 55% and 31% power delay product improvement at 40 nm and 90 nm respectively. From ITC (International Test Conference 99) benchmark circuit synthesis results, at 0.3 V the proposed library achieves up to 52% timing improvement and 53% power savings in the 40 nm technology node. OPEN ACCESSJ. Low Power Electron. Appl. 2013, 3 234

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Section: Sub-threshold Cell Sizing Methodologymentioning

confidence: 99%

Sub-Threshold Standard Cell Sizing Methodology and Library Comparison

Liu

Gyvez

Ashouei

2013

JLPEA

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“…After technological considerations, at architectural level, the smart device architecture also needs to be reconsidered for flexibility. Some industrial [7] [8] or academic [2] [5] [6] smart devices have been proposed, but targeting specific performances without providing a full applicative range capability. In [5], a full system is proposed in 180nm technology exhibiting only 15nW in standby and 304nW dynamic power for a motion detection application.…”

Section: Flexibility Requirements For Iot Devicesmentioning

confidence: 99%

“…As highlighted in Section 2, autonomous IoT devices recovering their energy form the environment can suffer from low voltage supplies. An interesting solution is to run at the Minimum Energy Point (MEP), defined as the operating voltage for which the total energy consumed per operation is minimized [2].…”

Section: Exploring Utbb Fdsoi At Near-threshold Voltagementioning

confidence: 99%

“…Well-known applications of the Internet of Things are requiring low performances (1-100MHz) and ultra-low leakage. They are thus using technology nodes from 180nm down to 65nm [1] [2]. This choice is justified by both cost and leakage power as those systems are most of their time asleep and wake up only once in a while [3].…”

Section: Introductionmentioning

confidence: 99%

“…However, as the technology cannot do all the job, a new versatile sub-system microcontrollers architectures is also proposed to fit a largest number of IoT applications as shown in Figure 1. Many smart devices or sub-system microcontrollers have been proposed [2], [5], [6], [7], [8] but they are covering only small segments of the speed/power performance spectrum required by IoT applications. Today, more and more applications are requiring both high performance for highly computational tasks and very low power consumption for simple tasks.…”

Section: Introductionmentioning

confidence: 99%

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UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels

Berthier

Beigné

Heitzmann

et al. 2016

Solid-State Electronics

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In this paper, we propose to analyze Ultra Thin Body and Box FDSOI technology suitability and architectural solutions for IoT applications and more specifically for autonomous Wireless Sensor Nodes (WSNs). As IoT applications are extremely diversified there is a strong need for flexible solutions at design, architectural level but also at technological level. Moreover, as most of those systems are recovering their energy from the environment, they are challenged by low voltage supplies and low leakage functionalities. We detail in this paper some Ultra Thin Body and Box FDSOI 28nm characteristics and results demonstrating that this technology could be a perfect option for multidisciplinary IoT devices. Back biasing capabilities and low voltage features are investigated demonstrating efficient high speed/low leakage flexibility. In addition, architectural solutions for WSNs microcontroller are also proposed taking advantage of Ultra Thin Body and Box FDSOI characteristics for full user applicative flexibility. A partioned architecture between an Always Responsive part with an asynchronous Wake Up Controller (WUC) managing WSN current tasks and an On Demand part with a main processor for application maintenance is presented. First results of the Always Responsive part implemented in Ultra Thin Body and Box FDSOI 28nm are also exposed.

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