SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-<i>μ</i>W/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode

Bol, David; Schramme, Maxime; Moreau, Ludovic; Xu, Pengcheng; Dekimpe, Rémi; Saeidi, Roghayeh; Haine, Thomas; Frenkel, Charlotte; Flandre, Denis

doi:10.1109/jssc.2021.3056219

Cited by 26 publications

(6 citation statements)

References 39 publications

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“…For B = 125 kHz, which is the typical bandwidth used in Europe [3], the minimum required frequency increases from 20.9 MHz to 23.2 MHz when increasing the SF from 7 to 9. Such frequencies are easily attained by ULP MCUs as they commonly have CPU frequencies in the range 32 -180 MHz [11]. We note that the minimum CPU frequency does not increase monotonically with the SF as the FFT implementation of the CMSIS library is more efficient for FFT sizes with an even power of two.…”

Section: Evaluation Of the Minimum Cpu Frequencymentioning

confidence: 90%

Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller

Xhonneux¹,

Louveaux²,

Bol³

2021

Preprint

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Internet-of-Things sensing applications rely on ultra low-power (ULP) microcontroller units (MCUs) that wirelessly transmit data to the cloud. Typical MCUs nowadays consist of generic blocks, except for the protocol-specific radios implemented in hardware. Hardware radios however slow down the evolution of wireless protocols due to retrocompatiblity concerns. In this work, we explore a software-defined radio architecture by demonstrating a LoRa transceiver running on custom ULP MCU codenamed SleepRider with an ARM Cortex-M4 CPU. In SleepRider MCU, we offload the generic baseband operations (e.g., low-pass filtering) to a reconfigurable digital front-end block and use the Cortex-M4 CPU to perform the protocol-specific computations. Our software implementation of the LoRa physical layer only uses the native SIMD instructions of the Cortex-M4 to achieve real-time transmission and reception of LoRa packets. SleepRider MCU has been fabricated in a 28nm FDSOI CMOS technology and is used in a testbed to experimentally validate the software implementation. Experimental results show that the proposed software-defined radio requires only a CPU frequency of 20 MHz to correctly receive a LoRa packet, with an ultra-low power consumption of 0.42 mW on average.

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Section: Evaluation Of the Minimum Cpu Frequencymentioning

confidence: 90%

Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller

Xhonneux¹,

Louveaux²,

Bol³

2021

Preprint

Self Cite

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“…Table 2 shows a comparison with recently published IoT end-nodes and fully programmable clusters. Compared to traditional single-core IoT end nodes [29], [30], the proposed work delivers significantly better performance and efficiency thanks to the exploitation of parallelism. Compared to similar fully programmable multi-core IoT endnodes [23], [31], implemented in 40nm and 22nm technology nodes, respectively, the proposed SoC delivers similar performance and energy efficiency on an 8-bit format, despite the less scaled technology node used for its implementation.…”

Section: Comparison With the State-of-the-artmentioning

confidence: 99%

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Ottavi¹,

Garofalo²,

Tagliavini³

et al. 2022

Preprint

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Computationally intensive algorithms such as Deep Neural Networks (DNNs) are becoming killer applications for edge devices. Porting heavily data-parallel algorithms on resource-constrained and battery-powered devices poses several challenges related to memory footprint, computational throughput, and energy efficiency. Low-bitwidth and mixed-precision arithmetic have been proven to be valid strategies for tackling these problems. We present Dustin, a fully programmable compute cluster integrating 16 RISC-V cores capable of 2-to 32-bit arithmetic and all possible mixed-precision permutations. In addition to a conventional Multiple-Instruction Multiple-Data (MIMD) processing paradigm, Dustin introduces a Vector Lockstep Execution Mode (VLEM) to minimize power consumption in highly data-parallel kernels. In VLEM, a single leader core fetches instructions and broadcasts them to the 15 follower cores. Clock gating Instruction Fetch (IF) stages and private caches of the follower cores leads to 38% power reduction with minimal performance overhead (< 3%). The cluster, implemented in 65 nm CMOS technology, achieves a peak performance of 58 GOPS and a peak efficiency of 1.15 TOPS/W.

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“…Compared to a traditional low-power programmable IoT system such as [35], representative of a wide range of low- cost microcontrollers embedding CortexM0, DARKSIDE delivers several orders of magnitude better integer (8-bit) peak performance and also 1.9× better energy efficiency, despite SleepRunner [35] is implemented in a more scaled technology node (28nm FD-SOI). Contrarily to DARKSIDE's cluster, the implementation strategy of SleepRunner is highly optimized to operate at very low voltage (i.e.…”

Section: Comparison With the State-of-the-artmentioning

confidence: 99%

DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training

Garofalo

Tortorella

Perotti³

et al. 2022

IEEE Open J. Solid-State Circuits Soc.

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On-chip DNN inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy and flexibility requirements. Heterogeneous clusters are promising solutions to meet the challenge, combining the flexibility of DSP-enhanced cores with the performance and energy boost of dedicated accelerators. We present DARKSIDE, a Systemon-Chip with a heterogeneous cluster of 8 RISC-V cores enhanced with 2-b to 32-b mixed-precision integer arithmetic. To boost performance and efficiency on key compute-intensive Deep Neural Network (DNN) kernels, the cluster is enriched with three digital accelerators: a specialized engine for low-data-reuse depthwise convolution kernels (up to 30 MAC/cycle); a minimal overhead datamover to marshal 1-b to 32-b data on-the-fly; a 16b floating point Tensor Product Engine (TPE) for tiled matrixmultiplication acceleration. DARKSIDE is implemented in 65nm CMOS technology. The cluster achieves a peak integer performance of 65 GOPS and a peak efficiency of 835 GOPS/W when working on 2-b integer DNN kernels. When targeting floatingpoint tensor operations, the TPE provides up to 18.2 GFLOPS of performance or 300 GFLOPS/W of efficiency -enough to enable on-chip floating-point training at competitive speed coupled with ultra-low power quantized inference.

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SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode

Cited by 26 publications

References 39 publications

Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller

Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training

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