SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management

Dekimpe, Rémi; Schramme, Maxime; Lefebvre, Martin; Kneip, Adrian; Saeidi, Roghayeh; Xhonneux, Mathieu; Moreau, Ludovic; Gonzalez, Marco; Pirson, Thibault; Bol, David

doi:10.23919/vlsicircuits52068.2021.9492365

Cited by 10 publications

(5 citation statements)

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“…We finally demonstrate and evaluate the LoRa and Sigfox SDRs in an experimental testbed. SleepRider MCU [13] is used in the testbed as a prototype of the microcontroller architecture introduced in Section II. In this section, we first describe our testbed.…”

Section: Experimental Performance Evaluation and Discussionmentioning

confidence: 99%

“…To minimize their power consumption, ULP MCUs often rely on low supply voltages, which also imply low CPU frequencies. As such, ULP MCUs usually exhibit minimum energy points below 50 MHz [13]. Overall, the Harvard architecture and the SIMD DSP instructions of the Cortex-M4 offer a 4.65× speed-up for the complex FFT compared to the M0, at the cost of a relative power consumption only 2.3× higher and a CPU area only 3.5× larger (for a 40LP technology) [14], [15].…”

Section: Cortex-m0mentioning

confidence: 99%

“…Fig. 4 shows the architecture of the proposed SDR-capable MCU, codenamed SleepRider [13]. The design contains an ARM Cortex-M4 CPU, two 32-kB high-density (HD) SRAM memories, a Direct Memory Access (DMA) controller, a custom digital front-end (DFE), a unified frequency and back-bias regulation (UFBBR) unit and I/O peripherals.…”

Section: Microcontroller Architecture With Digital Front-endmentioning

confidence: 99%

“…Except for the PMEM, the CPU and all other blocks share a single memory bus to exchange data. SleepRider MCU was designed for ULP consumption in 28nm FDSOI with various techniques, including ultra-low supply voltage (0.4V) for its logic [13]. The UFBBR unit jointly generates the main system clock and the back-bias voltages of the FDSOI transistors to compensate for PVT variations.…”

Section: Microcontroller Architecture With Digital Front-endmentioning

confidence: 99%

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A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios

Xhonneux

Louveaux

Bol

2023

IEEE Open J. Circuits Syst.

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We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra lowpower microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultralow power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 -332 µW) for the digital signal processing of the software-defined radios.INDEX TERMS Internet of Things, Wireless communications, Microcontrollers, Low-power wide area networks, Reconfigurable devices, Software defined radio.

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Section: Experimental Performance Evaluation and Discussionmentioning

confidence: 99%

Section: Cortex-m0mentioning

confidence: 99%

Section: Microcontroller Architecture With Digital Front-endmentioning

confidence: 99%

Section: Microcontroller Architecture With Digital Front-endmentioning

confidence: 99%

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A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios

Xhonneux

Louveaux

Bol

2023

IEEE Open J. Circuits Syst.

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“…We prototyped the architecture from Section III within the SleepRider MCU in 28nm FDSOI [12]. The fabricated MCU is integrated in a testbed to experimentally validate the proposed LoRa SDR LoRa and evaluate its performance.…”

Section: Experimental Performance Evaluationmentioning

confidence: 99%

Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller

Xhonneux¹,

Louveaux²,

Bol³

2021

Preprint

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Internet-of-Things sensing applications rely on ultra low-power (ULP) microcontroller units (MCUs) that wirelessly transmit data to the cloud. Typical MCUs nowadays consist of generic blocks, except for the protocol-specific radios implemented in hardware. Hardware radios however slow down the evolution of wireless protocols due to retrocompatiblity concerns. In this work, we explore a software-defined radio architecture by demonstrating a LoRa transceiver running on custom ULP MCU codenamed SleepRider with an ARM Cortex-M4 CPU. In SleepRider MCU, we offload the generic baseband operations (e.g., low-pass filtering) to a reconfigurable digital front-end block and use the Cortex-M4 CPU to perform the protocol-specific computations. Our software implementation of the LoRa physical layer only uses the native SIMD instructions of the Cortex-M4 to achieve real-time transmission and reception of LoRa packets. SleepRider MCU has been fabricated in a 28nm FDSOI CMOS technology and is used in a testbed to experimentally validate the software implementation. Experimental results show that the proposed software-defined radio requires only a CPU frequency of 20 MHz to correctly receive a LoRa packet, with an ultra-low power consumption of 0.42 mW on average.

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