Sizing and characterization of leakage-control cells for layout-aware distributed power-gating

Babighian, P.; Benini, Luca; Macii, E.

doi:10.1109/date.2004.1268947

Cited by 9 publications

(5 citation statements)

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“…Some methods proposed to take advantage of available free resources to reduce the area cost of sleep transistors. For example, [15] used white spaces to insert sleep transistors; while others proposed to use dedicated rows [6,10,13] to place sleep transistors in the standard cell design. [16] proposed a general method for the physical design of sleep transistors under the context of a distributed model on power/ground network.…”

Section: Physical Design Of Sleep Transistorsmentioning

confidence: 99%

Techniques of Power-gating to Kill Sub-Threshold Leakage

Long

Xiong

Liu

2006

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

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Sub-threshold leakage has increased dramatically with technology scaling, and it already consumes a significant portion of the total power budget in current high-end chip designs. This paper presents a state-of-the-art overview of the power gating techniques that promise to reduce sub-threshold leakage power by up to three orders of magnitude. By emphasizing the challenges and up-to-date solutions, this paper provides an in-depth vision of the current status of powergating techniques. By analyzing the historic development of power-gating, this paper also outlines possible future evolution courses of the technique.

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Section: Physical Design Of Sleep Transistorsmentioning

confidence: 99%

Techniques of Power-gating to Kill Sub-Threshold Leakage

Long

Xiong

Liu

2006

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

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“…Image noise reduction is a fundamental task in image processing, which aims to remove unwanted noise from digital images while preserving important image details. Noise in digital images can arise from various sources such as sensor noise, environmental noise, or transmission noise [1,2]. The presence of noise can significantly degrade the quality and accuracy of the images, making them difficult to analyze and interpret.…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Analysis of Image Noise Reduction using XOR-Based Filtering Technique

2023

IRJMETS

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Image noise reduction is a critical problem in image processing, as it affects the quality and accuracy of the images. The XOR-based filtering technique has emerged as a promising approach to address this issue in recent years. This technique employs the XOR operation to remove noise from the images while preserving the important image details. This research paper comprehensively analyses the XOR-based filtering technique for image noise reduction. We evaluate the performance of this technique on various image datasets and compare it with other state-of-the-art image denoising techniques. Our experimental results show that the XOR-based filtering technique outperforms other methods in terms of both objective and subjective image quality metrics. Our experimental results demonstrate that the XOR-based filtering technique achieves superior performance in terms of peak signal-to-noise ratio (PSNR), structural similarity index (SSIM), and mean opinion score (MOS) compared to other denoising techniques. We also observe that the performance of the XOR-based filtering technique is consistent across different types of image noise, such as Gaussian, salt and pepper, and speckle noise.Furthermore, we conduct a parameter analysis of the XOR-based filtering technique to determine the optimal parameter values for different noise levels. Our results show that the XOR-based filtering technique is robust and can adapt to various noise levels.

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“…Sleep transistors are inserted on a row-by-row basis, at the boundaries of each row, as shown in Figure 1, and they are connected to a common virtual ground. The sleep transistors are picked from a library that contains devices of different sizes, driving strengths and speed, fully compliant with the cells belonging to the technology library; the sleep transistor cells in the library have been designed and fully characterized using the procedure of [10]. The number and the position of the cells driven by each sleep transistor is selected through the algorithm described in Section 4, which accounts for the area and delay overhead that are allowed through a user specification.…”

Section: Automatic Sti Methodologymentioning

confidence: 99%

“…These cells are inserted at the boundaries of existing cell rows, causing minimal disruption in placement and routing. Selection of the most appropriate sleep transistor cell size to control each group of cells is driven by the models of [10]. Furthermore, we present a novel gate clustering algorithm that groups together sets of cells to be controlled by the same sleep transistor; the cost function used by the algorithm to select the cells that have to be gated is layout-aware, i.e., it takes advantage of cell placement information.…”

Section: 1mentioning

confidence: 99%