Six-stage digital free-space optical switching network using symmetric self-electro-optic-effect devices

Abstract

We describe the design and demonstration of an extended generalized shuffle interconnection network, centrally controlled by a personal computer. A banyan interconnection pattern is implemented by use of computer-generated Fourier holograms and custom metallization at each 32 × 32 switching node array. Each array of electrically controlled tristate symmetric self-electro-optic-effect devices has 10,240 optical pinouts and 32 electrical pinouts, and the six-stage system occupies a 9 in. × 12.5 in. (22.9 cm × 31.7 cm) area. Details of the architecture, optical and mechanical design, and system alignment and tolerancing are presented.

Rationale and challenges for optical interconnects to electronic chips

“…The emergence of electrically controlled optical modulators based on novel effects in quantum-well structures [36], including the family of devices known as self-electrooptic-effect devices (SEED's) [37], [38] and the development of vertical-cavity surface-emitting lasers (VCSEL's) (see, e.g., [39] and [40] for recent representative examples), were particularly important because they offered viable optoelectronic output devices for fabrication in large numbers in arrays. The optoelectronic device arrays and smart pixels stimulated significant work on array optical systems (see, e.g., [41]), leading to some large system demonstrations based on the SEED technology with, e.g., tens of thousands of light beams in a functioning digital system [42].…”

“…Many of these techniques have been recently reviewed in [49]. References [28], [42], and [50]- [59] give examples of free-space systems investigated for optical interconnect applications. Waveguides on silicon chips have been investigated [60]- [62], though complete systems using these are not yet demonstrated.…”

“…They have successfully been made in large arrays that have also been solder bonded to the circuits. Their performance has been good enough to allow demonstration of large optically interconnected laboratory systems (see, e.g., [42], [48], [58], and [113]). When integrated with CMOS, the quantum-well technology is sometimes described as CMOS-SEED or optoelectronic VLSI.…”

Reconfigurable intelligent optical backplane for parallel computing and communications

“…Although a challenge, this is within the capabilities of current optomechanical technology. 23 A full diffractive-based analysis of the alignment tolerances of a clustered-window relay will be the subject of a later publication.…”

OMRAM and ODSP Smart Pixel Chipset Development

“…Moreover, several research groups are building system prototypes of such optoelectronic MINs 13 . For example, we have designed an optoelectronic perfect shuffle MIN and shown that this design outperforms both chip-level and multichip module (MCM) level be used).…”