SIS wide-band model extraction methodology for SOI on-chip inductor

Abstract

On-chip inductors are recently in high demand even for digital applications due to strict jitter and phase noise requirements in oscillators. Accurate and fast modeling techniques are needed to enable low-cost and fast silicon turnaround. We present a fast and accurate methodology named scaled, iterative, and sampled (SIS) non-linear least squares optimization to extract wide-band model parameters suitable up to 20 GHz for inductor. To test our methodology, we implement a silicon-on-insulator (SOI) inductor in a 45 nm technology. The inductor is suitable for 8 to 20 GHz operation with 1.45 nH inductance and a quality factor of 17 at 10 GHz. We correlate our results to silicon measurements and achieve a very good fit between our models and silicon data. With our methodology, we achieve modelturnaround time of a few hours.