SiO2/SiC structures annealed in D218O: Compositional and electrical effects

Pitthan, E.; Corrêa, Silma Alberton; Soares, Gabriel Vieira; Boudinov, H.; Stedile, Fernanda Chiarello

doi:10.1063/1.4869124

Cited by 5 publications

(3 citation statements)

References 32 publications

(43 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Bars represent an overall experimental inaccuracy of 10%. with previous findings, 22 as shown in Table I. Moreover, NRP data and simulations shown in Fig.…”

Section: Resultssupporting

confidence: 90%

Unraveling the mechanisms responsible for the interfacial region formation in 4H-SiC dry thermal oxidation

Dartora

Pitthan

Stedile

2017

Journal of Applied Physics

Self Cite

View full text Add to dashboard Cite

Aiming to understand the processes involved in the formation of the transition region between SiO 2 and SiC, known as the interfacial region, early steps of SiC oxidation were investigated using mainly nuclear reaction analyses. Oxidation kinetics reveals that an abrupt change in the oxidation mechanism is observed in C-face oxide films when their thickness is around 10 nm, while a continuous change in the oxidation mechanism is observed in Si-face oxide films with thicknesses up to about 4 nm. This last thickness corresponds to the maximum width of the interfacial region. Changes observed in the oxidation mechanism were related to oxidation reaction and interfacial atom emission that may take place during oxide film growth. Besides, the activation energies of such processes were obtained.

show abstract

“…Bars represent an overall experimental inaccuracy of 10%. with previous findings, 22 as shown in Table I. Moreover, NRP data and simulations shown in Fig.…”

Section: Resultssupporting

confidence: 90%

Unraveling the mechanisms responsible for the interfacial region formation in 4H-SiC dry thermal oxidation

Dartora

Pitthan

Stedile

2017

Journal of Applied Physics

Self Cite

View full text Add to dashboard Cite

show abstract

“…Concerning the formation of positive charge due to the CO interaction, it could be an effect from the oxygen exchange between the CO and the oxide film, 20 or the modification in the oxide/semiconductor interfacial region during the annealing (as will be presented and discussed below). A similar oxygen exchange, between the gas and the solid phase, in all depths of the oxide film was already observed in SiO 2 /SiC samples annealed in D 2 18 O, 24 but no positive charge was induced. Thus, it is more likely that the positive charge originates from modifications in the interfacial region due to the CO annealing.…”

supporting

confidence: 73%

Influence of CO annealing in metal-oxide-semiconductor capacitors with SiO2 films thermally grown on Si and on SiC

Pitthan

Reis

Corrêa

et al. 2016

Journal of Applied Physics

Self Cite

View full text Add to dashboard Cite

Understanding the influence of SiC reaction with CO, a by-product of SiC thermal oxidation, is a key point to elucidate the origin of electrical defects in SiC metal-oxide-semiconductor (MOS) devices. In this work, the effects on electrical, structural, and chemical properties of SiO2/Si and SiO2/SiC structures submitted to CO annealing were investigated. It was observed that long annealing times resulted in the incorporation of carbon from CO in the Si substrate, followed by deterioration of the SiO2/Si interface, and its crystallization as SiC. Besides, this incorporated carbon remained in the Si surface (previous SiO2/Si region) after removal of the silicon dioxide film by HF etching. In the SiC case, an even more defective surface region was observed due to the CO interaction. All MOS capacitors formed using both semiconductor materials presented higher leakage current and generation of positive effective charge after CO annealings. Such results suggest that the negative fixed charge, typically observed in SiO2/SiC structures, is not originated from the interaction of the CO by-product, formed during SiC oxidation, with the SiO2/SiC interfacial region.

show abstract

“…It should be noted that such an improvement is possibly due to the presence of hydrogen introduced from H 2 O during wet annealing, as typically observed in oxide semiconductor thin film transistors 64 and SiC MOS devices. 65 The contribution of hydrogen to the obtained findings is expected in the current system. Consequently, we achieved a mostly midgap peak-free D it distribution, which is atypical for GaAs MOS systems, owing to the presence of moderate AlN passivation and PDA optimizations.…”

Section: E Optimization Of Pda Conditionsmentioning

confidence: 64%

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

et al. 2015

View full text Add to dashboard Cite

This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm−2 eV−1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

show abstract

SiO2/SiC structures annealed in D218O: Compositional and electrical effects

Cited by 5 publications

References 32 publications

Unraveling the mechanisms responsible for the interfacial region formation in 4H-SiC dry thermal oxidation

Unraveling the mechanisms responsible for the interfacial region formation in 4H-SiC dry thermal oxidation

Influence of CO annealing in metal-oxide-semiconductor capacitors with SiO2 films thermally grown on Si and on SiC

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

Contact Info

Product

Resources

About