Single-track handshake signaling with application to micropipelines and handshake circuits

Berkel, Kees van; Bink, Arjan

doi:10.1109/async.1996.494444

Cited by 45 publications

(27 citation statements)

References 6 publications

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“…The single-track handshake protocol, as described by Van Berkeland Bink [9], combines the advantages of two-and four-phase handshaking. It has the minimum number of transitions, that is, two per handshake, and after each handshake the initial state is restored.…”

Section: Single Trackmentioning

confidence: 99%

Single-rail handshake circuits

Peeters

Berkel

Proceedings Second Working Conference on Asynchronous Design Methodologies

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111

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Section: Single Trackmentioning

confidence: 99%

Single-rail handshake circuits

Peeters

Berkel

Proceedings Second Working Conference on Asynchronous Design Methodologies

Self Cite

111

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“…Single-track handshake [van Berkel and Bink 1996] protocol tries to overcome this weakness of four phase protocol by practically eliminating the neutrality phase. Figure 3 shows an overview of a single-track handshake protocol.…”

Section: Four Phase Handshake Vs Single-track Handshakementioning

confidence: 99%

“…To circumvent the problem of high handshake overhead, we present two novel pipeline templates, which greatly minimize the handshake circuitry by taking advantage of some easily satisfiable timing assumptions. Our proposed pipelines use single-track handshake protocols [van Berkel and Bink 1996]. Logic density is enhanced by packing multiple logic stages in a single pipeline, while still maintaining a very fast cycle time of 18 transitions.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits

Sheikh

Manohar

2011

J. Emerg. Technol. Comput. Syst.

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We present two novel energy-efficient pipeline templates for high throughput asynchronous circuits. The proposed templates, called N-P and N-Inverter pipelines, use single-track handshake protocol. There are multiple stages of logic within each pipeline. The proposed techniques minimize handshake overheads associated with input tokens and intermediate logic nodes within a pipeline template. Each template can pack significant amount of logic in a single stage, while still maintaining a fast cycle time of only 18 transitions. Noise and timing robustness constraints of our pipelined circuits are quantified across all process corners. A completion detection scheme based on wide NOR gates is presented, which results in significant latency and energy savings especially as the number of outputs increase. To fully quantify all design trade-offs, three separate pipeline implementations of an 8x8-bit Booth-encoded array multiplier are presented. Compared to a standard QDI pipeline implementation, the N-Inverter and N-P pipeline implementations reduced the energy-delay product by 38.5% and 44% respectively. The overall multiplier latency was reduced by 20.2% and 18.7%, while the total transistor width was reduced by 35.6% and 46% with N-Inverter and N-P pipeline templates respectively.

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“…Various ways to implement handshaking have been identified and developed throughout the years, most of these using a separate request and acknowledge wire, on which events strictly alternate and are interpreted in either a four-phase or a two-phase manner [5,16,171. More exotic implementations of handshaking have also been also been proposed, such as single-track [2] (in which request and acknowledge events are mapped onto the same wire) and pulse-mode [7,14,151 (in which separate request and acknowledge pulses are used, which are generally non-overlapping).…”

Section: Sample-based Handshake Protocolsmentioning

confidence: 99%