Single reference continuous rate clock and data recovery from 30 Mbit/s to 3.2 Gbit/s

Frambach, J.-P.; Heijna, R.; Krosschell, R.

doi:10.1109/cicc.2002.1012847

Cited by 4 publications

(3 citation statements)

References 1 publication

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“…Most reported PRBS generators in the gigabit range have been realized using III-V, bipolar, or HBT technologies [1] [2]. Devices in these technologies typically require large voltage drops across them, leading to the need for supplies that are greater than 2.5 V. This increased supply voltage eases headroom concerns in the circuit design, but also results in higher power consumption.…”

Section: Prbs Generatormentioning

confidence: 99%

Design of a 5-Gb/s PRBS generator in 0.18μm CMOS process

Lee

Weber

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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High frequency CMOS design techniques, with attention to design for test, were used to create a 5-Gb/s 2^7-1 pseudo-random bit sequence generator (PRBS) for high-speed digital signal test in a standard 0.18µm CMOS technology. The design utilized optimized current mode logic (CML) cells to realize the digital logic functions as well as inductively peaked output drivers to maximize circuit bandwidth. The design was verified both through Spectre simulations and lab measurements.

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Section: Prbs Generatormentioning

confidence: 99%

Design of a 5-Gb/s PRBS generator in 0.18μm CMOS process

Lee

Weber

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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“…One is the multirate CDR circuit with multiple reference clocks [2] or single reference clock with a programmable divider [3] or without reference clock [4,5]. The other is the continuous-rate CDR circuit with fractional-N divider [6] or without an external reference clock [7][8][9][10]. The latter CDR scheme detects a change in the bit rate of the incoming data and adaptively controls the internal widerange VCO to track the bit rate without harmonic-lock issue.…”

Section: Introductionmentioning

confidence: 99%

A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition

Lee

Kim

Park

et al. 2011

Journal of Electrical and Computer Engineering

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“…Compared with multirate CDR circuits, the continuous-rate CDR circuits can detect various bit rates over a wide range. However, a complex frequency detection circuit would be required, such as a frequency synthesizer [4] or a time-to-digital converter [5].…”

Section: Introductionmentioning

confidence: 99%

A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit

Yang

Chao

Hwu

et al. 2006

IEEE J. Solid-State Circuits

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A 200-Mbps 2-Gbps continuous-rate clock-anddata-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2 31 1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10 12 . The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.

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Single reference continuous rate clock and data recovery from 30 Mbit/s to 3.2 Gbit/s

Cited by 4 publications

References 1 publication

Design of a 5-Gb/s PRBS generator in 0.18μm CMOS process

Design of a 5-Gb/s PRBS generator in 0.18μm CMOS process

A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition

A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit

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