Single-package direct-conversion receiver for 802.11a wireless LAN enhanced with fast converging digital compensation techniques

Côme, B.; Hauspie, D.; Albasini, G.; Brebels, S.; Raedt, W. De; Diels, W.; Eberle, Wolfgang; Minami, Hideki; Ryckaert, Julien; Tubbax, J.; Donnay, S.

doi:10.1109/mwsym.2004.1336040

Cited by 9 publications

(10 citation statements)

References 6 publications

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“…[15] suggests an architecture adding a digitally controlled complex compensation DC-offset directly after the mixer. Building on similar architectural approach, [5,12] presents characterization algorithms that find the optimal complex compensation DC-value while keeping the system operational. Both techniques provide very fast convergence and are thus applicable in the multi-mode transceivers.…”

Section: Dc-offsetmentioning

confidence: 99%

Wireless System and Circuit Design Space in Modern Digital CMOS Technology

Oliveira

Goes

2011

Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies

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The ultimate dream of every Software-Defined Radio (SDR) front-end designer is to deliver an RF transceiver that can be reconfigured into every imaginable operating mode, in order to comply with the requirements of all existing and even upcoming communication standards. These include a large range of modes for cellular (2G-2.5G-3G and further), WLAN (802.11a/b/g/n), WPAN (Bluetooth, Zigbee, ...), broadcasting (DAB, DVB, DMB, ...) and positioning (GPS, Galileo) functionality. Obviously, all of them have different center frequency, channel bandwidth, noise levels, interference requirements, transmit spectral mask, etc. As a consequence, the performances of all building blocks in the transceiver must be reconfigurable over an extremely wide range, requiring ultimate creativity from the SDR designer.Reconfigurability is a requirement for SDR functionality, but often one forgets that it can also be an enabler for low power consumption. Indeed, once the flexibility is built into the transceiver, it can be used to adapt the performance of the radio to the actual circumstances, instead of those implied by the worst-case situation of the standard. Since linearity, filtering, noise, bandwidth, etc. can be traded for power consumption in the SDR, a smart controller is able to adapt the radio at runtime to the actual performance required, and hence can reduce the average power consumption of the SDR.In this chapter, several important innovations and concepts will be presented that bring this ultimate dream closer to reality. These include circuits for wideband LO synthesis, multifunctional receiver and transmitter blocks, novel ADC implementations, etc. The result of this all is integrated in the world's first SDR transceiver covering the frequency range from 174 MHz to 6 GHz, implemented in a 1.2V 0.13 μm CMOS technology.

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Section: Dc-offsetmentioning

confidence: 99%

Wireless System and Circuit Design Space in Modern Digital CMOS Technology

Oliveira

Goes

2011

Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies

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show abstract

“…Reference [27] suggests an architecture adding a digitally controlled complex compensation dc offset directly after the mixer. Building on a similar architectural approach, several authors [25,28] present characterization algorithms that find the optimal complex compensation dc value while keeping the system operational. Both techniques provide very fast convergence and are thus applicable in multi-mode transceivers.…”

Section: Offsetmentioning

confidence: 99%

Software‐Defined Radio Front Ends

Hueber¹,

Staszewski

2010

Multi‐Mode/Multi‐Band RF Transceivers for Wireless Communications

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The ultimate dream of every software-defined radio (SDR) front-end architect is to deliver a radio-frequency (RF) transceiver that can be reconfigured into every imaginable operating mode, in order to comply with the requirements of all existing and even upcoming communication standards. These include a large range of modes for cellular (2G-2.5G-3G and further), WLAN (802.11a/b/g/n), WPAN (Bluetooth, Zigbee, etc.), broadcasting (DAB, DVB, DMB, etc.), and positioning (GPS, Galileo) functionalities. Obviously, each of them has different center frequency, channel bandwidth, noise levels, interference requirements, transmit spectral mask, and so on. As a consequence, the performances of all building blocks in the transceiver must be reconfigurable over an extremely wide range, requiring ultimate creativity from the SDR designer.Reconfigurability is a requirement for SDR functionality, but often one forgets that it can also be an enabler for low power consumption. Indeed, once flexibility is built into a transceiver, it can be used to adapt the performance of a radio to the actual circumstances instead of those implied by the worst-case situation of the standard. Since linearity, filtering, noise, bandwidth, and so on, can be traded for power consumption in the SDR, a smart controller is able to adapt the radio at runtime to the actual performance required, and hence can reduce the average power consumption of the SDR.In this chapter, several important innovations and concepts are presented that bring this ultimate dream closer to reality. These include circuits for wideband local oscillator (LO) synthesis, multifunctional receiver and transmitter blocks, and novel ADC (analog-to-digital converter) implementations. The result of all this is integrated in the world's first SDR transceiver covering the frequency range from 174 MHz to 6 GHz, implemented in a 1.2-V 0.13-µm CMOS technology.

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“…Haspeslagh et al (1992) suggest an architecture adding a digitally controlled complex compensation DC offset directly after the mixer. Building on similar architectural approach (Come et al, 2004;Debaillie, 2007) present characterization algorithms that find the optimal complex compensation DC value while keeping the system operational. Both techniques provide very fast convergence and are thus applicable in the multimode transceivers.…”

Section: Offsetmentioning

confidence: 99%