Single machine scheduling subject to precedence delays

Instruction Scheduling with Release Times and Deadlines on ILP Processors

“…By using induction and the properties of forward scheduling and backward scheduling, we can prove the fol- v [5,12] v [6,15] v [6,15] v [8,15] 6 v [6, 15] v [8,10] v [8,10] v [4,8] v [5,13] v [2,6] v [3,7] Proof Suppose that there exists a feasible schedule σ ′ , but a schedule σ computed by our algorithm is not feasible. Let v k be the first late instruction and t the earliest integer time point satisfying 1) there are m k (σ(v k ) − t) instructions scheduled in the time interval [t, σ(v k )) on m k functional unit of type R(v k ) in σ, where m k is the number of functional units of type R(v k ), and 2) for each instruction …”

“…In non-real-time applications, the objective of instruction scheduling is to find a shortest schedule for a set of instructions. This problem is NP-complete even if the target processor has only one functional unit and latencies can be arbitrarily large [12,13].…”

“…Suppose that our algorithm has computed the 0-successortree consistent deadline of v 6 which is 7, we show how our algorithm computes the 4-successor-tree-consistent dead- [5,13] v [8,10] v [8,10] v [4,8] v [5,12] v [2,6] v [1,4] Lastly it applies disjoint union-find algorithm to find the successor-tree-consistent deadline which is 11. The l max (v i )-successor-tree-consistent deadline of each instruction v i is shown in Figure 6 where y in [x, y] beside each instruction v i is the l max (v i )-successor-tree-consistent deadline of v i .…”

“…As a result, no feasible exists for the original problem instance P (v i ). v [3,14] v [3,12] v [3,15] v [5,15] v [5,15] v [5,12] v [6,15] v [6,15] v [5,14] v [8,15] v [3,10] 6 v [6, 15] v [8,10] v [8,10] v [4,9] v [2,6] Figure 2. The edge-consistent release times and deadlines in P Example 1 Consider a problem instance P with 14 instructions and an ILP processor with two heterogeneous functional units F 1 and F 2 .…”

An integer programming approach to optimal basic block instruction scheduling for single-issue processors

“…The starting times of dependent instructions must obey these latencies to ensure that no conflicts occur and all operands are present in logic when they execute. These precedence and latency constraints make instruction scheduling an N P-hard combinatorial optimization problem [2], even for single-issue processors that allow only at most one instruction to be inserted into the pipeline (issued ) in every clock cycle. Polynomial-time solvability is known only for the very restrictive case that the maximum occurring latency is one clock cycle [3].…”