Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction

Kumar, Rakesh; Farkas, Keith I.; Jouppi, Norman P.; Ranganathan, Parthasarathy; Tullsen, Dean M.

doi:10.1109/micro.2003.1253185

Cited by 415 publications

(442 citation statements)

References 26 publications

(22 reference statements)

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“…(3) With known job characteristics, complementary job allocation is applied to maximize the server utilization while avoiding resource bottlenecks (e.g., memory-intensive jobs and CPU-intensive jobs are allocated to the same server [35]). (4) If a single job has different phases [21,30,31], such as parallel phases and sequential phases, schedulers map the sequential phase on a high-performance core and the parallel phase on a number of energy-efficient cores.…”

Section: Related Workmentioning

confidence: 99%

A Theoretical Foundation for Scheduling and Designing Heterogeneous Processors for Interactive Applications

Ren

McKinley

2014

Lecture Notes in Computer Science

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To improve performance and meet power constraints, vendors are introducing heterogeneous multicores that combine high performance and low power cores. However, choosing which cores and scheduling applications on them remain open problems. This paper presents a scheduling algorithm that provably minimizes energy on heterogeneous multicores and meets latency constraints for interactive applications, such as search, recommendations, advertisements, and games. Because interactive applications must respond quickly to satisfy users, they impose multiple constraints, including average, tail, and maximum latency. We introduce SEM (Slow-to-fast, Energy optimization for Multiple constraints), which minimizes energy by choosing core speeds and how long to execute jobs on each core. We prove SEM minimizes energy without a priori knowledge of job service demand, satisfies multiple latency constraints simultaneously, and only migrates jobs from slower to faster cores. We address practical concerns of migration overhead and congestion. We prove optimizing energy for average latency requires homogeneous cores, whereas optimizing energy for tail and deadline constraints requires heterogeneous cores. For interactive applications, we create a formal foundation for scheduling and selecting cores in heterogeneous systems.

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Section: Related Workmentioning

confidence: 99%

A Theoretical Foundation for Scheduling and Designing Heterogeneous Processors for Interactive Applications

Ren

McKinley

2014

Lecture Notes in Computer Science

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“…The first is at the computer architecture level, techniques have been proposed to reduce processor energy usage through multi-core processors [34], designing energy proportional hardware [20], and increasing the number of performance and sleep states [41]. Benchmarking techniques to quantify the energy costs of different computer architectures have been proposed [48].…”

Section: State Of the Artmentioning

confidence: 99%

From the Origins of Performance Evaluation to New Green ICT Performance Engineering

Juiz

Puigjaner

2011

Performance Evaluation of Computer and Communication Systems. Milestones and Future Challenges

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Abstract. This paper intends to present an overview of the evolution of performance evaluation since its first steps the Erlang works for modelling telephone networks, based on simple queues until the present current challenges in Green ICT that will require the development of new paradigms and mathematical tools, and rapidly passing across the modelling works of Khintchine and Pollaczeck; Jackson; Baskett, Chandy, Muntz and Palacios; Buzen; Reiser and Lavenberg; and many others, and benchmarking standards that have produced solutions to the problems appearing in these hundred of years. Finally, we analyze some of the challenges of computer performance evaluation appearing today, mainly those related to the energy consumption and sustainability, globally known as Green ICT.

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“…Understanding this effect is crucial for building efficient multicore scheduling algorithms. Many of these algorithms (aiming to improve performance [2,6,9,13], reduce energy consumption [8] or improve thermal regulation [4,12]) work via frequent migrations of processes among CPU cores. Frequent migrations prevent the scheduler from exploiting cache affinity and may thus hurt performance.…”

Section: Introductionmentioning

confidence: 99%

Performance Implications of Cache Affinity on Multicore Processors

Kazempour

Fedorova

Alagheband

2008

Lecture Notes in Computer Science

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Abstract. Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity is exploited by OS schedulers: they tend to reschedule processes to run on a recently used processor. On conventional (unicore) multiprocessor systems, exploitation of cache affinity improves performance. It is not yet known, however, whether similar performance improvements would be observed on multicore processors. Understanding these effects is crucial for design of efficient multicore scheduling algorithms. Our study analyzes performance effects of cache affinity exploitation on multicore processors. We find that performance improvements on multicore uniprocessors are not significant. At the same time, performance improvements on multicore multiprocessors are rather pronounced.

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Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction

Abstract: Abstract

Cited by 415 publications

References 26 publications

A Theoretical Foundation for Scheduling and Designing Heterogeneous Processors for Interactive Applications

A Theoretical Foundation for Scheduling and Designing Heterogeneous Processors for Interactive Applications

From the Origins of Performance Evaluation to New Green ICT Performance Engineering

Performance Implications of Cache Affinity on Multicore Processors

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