Single-graph multiple flows: Energy efficient design alternative for GPGPUs

Abstract

We present the single-graph multiple-flows (SGMF) architecture that combines coarse-grain reconfigurable computing with dynamic dataflow to deliver massive thread-level parallelism. The CUDA-compatible SGMF architecture is positioned as an energy efficient design alternative for GPGPUs.The architecture maps a compute kernel, represented as a dataflow graph, onto a coarse-grain reconfigurable fabric composed of a grid of interconnected functional units. Each unit dynamically schedules instances of the same static instruction originating from different CUDA threads. The dynamically scheduled functional units enable streaming the data of multiple threads (or graph flows, in SGMF parlance) through the grid. The combination of statically mapped instructions and direct communication between functional units obviate the need for a full instruction pipeline and a centralized register file, whose energy overheads burden GPGPUs.We show that the SGMF architecture delivers performance comparable to that of contemporary GPGPUs while consuming ∼57% less energy on average.

Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays

“…Such accesses can be attributed to two major causes: using the memory (global or local) for interthread communication, and having multiple threads access the same memory locations. In this paper we introduce direct inter-thread communication to the previously proposed multithreaded coarse-grain reconfigurable array (MT-CGRA) [6,7]. The proposed dMT-CGRA architecture eliminates redundant memory accesses by allowing threads to directly communicate through the CGRA fabric.…”

“…The MT-CGRA execution model combines the static and dynamic dataflow models to execute single-instruction multiple-threads (SIMT) programs with better performance and power characteristics than von Neumann GPGPUs [6]. The model converts SIMT kernels into dataflow graphs and maps them to the CGRA fabric, where each functional unit multiplexes its operation on tokens from different instances of a dataflow graph (i.e., threads).…”

“…Nevertheless, neither of these architecture support simultaneous dynamic dataflow execution of threads on the same grid. While, SGMF [6] and VGIW [7] do support simultaneous dynamic multithreaded execution on the same grid, they do not support inter thread communication between threads.…”

“…Seeking an alternative to the von Neumann GPGPU model, both the research community and industry began exploring dataflow-based systolic and coarse-grained reconfigurable architectures (CGRA) [1][2][3][4][5]. As part of this push, Voitsechov and Etsion introduced the massively multithreaded CGRA (MT-CGRA) architecture [6,7], which maps the compute graph of CUDA kernels to a CGRA and uses the dynamic dataflow execution model to run multiple CUDA threads. The MT-CGRA architecture leverages the direct connectivity between functional units, provided by the CGRA fabric, to eliminate multiple von Neumann bottlenecks including the register file and instruction control.…”

Ultra low latency dataflow renderer

“…The dataflow co-processor in their system did not drive a display directly, but performed pre-processing on 3D data, a function not dissimilar to modern day vertex or geometry shaders. Voitsechov & Etsion present an alternative architecture for GPGPUs based on dataflow computing [15]. In their architecture instructions from CUDA kernels are mapped to a dataflow graph.…”