Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

Abstract

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

Impact of Gate Metal Work-function for On-to-off Current Ratio and Threshold Voltage in Junctionless Gate-All-Around (GAA) MOSFET Stacked with SiO2 and High-k Dielectric

“…It can be seen that the contour lines of the threshold voltage 0.9 V and the on-to-off current ratio 10 15 are almost identical, so that the on-to-off current ratio can be maintained at 10 15 when the threshold voltage is 0.9 V at any gate metal work-function and the silicon radius. When the channel doping concentration is relatively small (10 18 /cm 3 ), the gate metal work-function is almost constant even if the silicon radius is increased to maintain the threshold voltage of 0.9 V and the on-to-off current ratio of 10 15 . The threshold voltage of 0.9 V and the on-to-off current ratio of 10 15 were maintained, which should increase the gate metal's work-function as the silicon radius increased.…”

“…When the channel doping concentration is relatively small (10 18 /cm 3 ), the gate metal work-function is almost constant even if the silicon radius is increased to maintain the threshold voltage of 0.9 V and the on-to-off current ratio of 10 15 . The threshold voltage of 0.9 V and the on-to-off current ratio of 10 15 were maintained, which should increase the gate metal's work-function as the silicon radius increased.…”

“…The JLFET has the advantage of simplifying the fabrication process and increasing oncurrent by fabricating the channel, source, and drain with the same kind of impurities and doping concentration [12]. As for the GAA structure, the rectangular-structured Omega-FETs and the triangular-and cylindrical-structured FETs have been studied [13][14][15]. In particular, it is known that by using the JL structure and the GAA structure in parallel, it is possible to not only solve the simple fabrication process but also to further decrease short channel effects (SCEs), compared to the junction-based structure [16].…”

Source/Drain Activation for Flexible Poly-Si Nanoscale pFETs with a Laser-Buffer Layer by CO2 laser Annealing

“…In one of our previous study, S/D activation for the poly-Si channel on a SiO 2 /Si substrate was performed with a laser-energy of 125 W and at T sub = 350 °C. 25 In this study, the SiO 2 /W/SiO 2 LBL with λ SiO2 = 900 nm was selected for the fabrication of nano-fFETs, and optimal S/D activation was conducted at T sub = 150 °C using CO 2 laser annealing with MELE = 15 W. The dielectric-layer and poly-Si/ dielectric-layer interface can be protected by TiN without suffering from laser deterioration. Moreover, the top-SiO 2 layer underneath the gate region is unable to absorb the CO 2 laser, so that the thermal impact on poly-Si/dielectric-layer and dielectric layer will be insignificant.…”