Single-fault fault collapsing analysis in sequential logic circuits

Chen, J.E.; Lee, Chung Len; Shen, Wen Zen

doi:10.1109/test.1990.114098

Cited by 8 publications

(7 citation statements)

References 5 publications

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“…A fault is a potentially detectable fault (PDF) if the fault is sequentially undetectable and, for every DFF, starting at the X state, there is an input sequence that produces a combination of the good and faulty output responses O/X or 1/X at some primary outputs [20]. From the previous discussion, the fault effect of the Case 1 fault on the propagation path is either O/X or 1/X which can not be considered to be detected when it propagates to the primary output.…”

Section: Resultsmentioning

confidence: 99%

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A two-phase fault simulation scheme for sequential circuits

Lee²,

Chen³

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

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A two-phase fault simulation scheme for sequential circuits is proposed. The scheme is done by first performing the true value simulation with several initial patterns and then by performing the fault simulation with the rest of patterns. With this fault simulation approach, some faults which consume much simulation time can be easily and quickly identified and dropped early. As a result, significant speedup on simulation time is obtained. Five cases of faults which cause problems in fault simulation are also discussed.

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Section: Resultsmentioning

confidence: 99%

“…Case 2: This case is caused by the sequential self-masking effect [20]. The circuit in Figure 4 is used to demonstrate this.…”

Section: Resultsmentioning

confidence: 99%

A two-phase fault simulation scheme for sequential circuits

Lee²,

Chen³

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

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“…In the latter case, all single stuck-at faults on gate inputs and outputs are injected and g-equivalent [28] faults are collapsed. An optional random ATPG phase is also We applied our method on three asynchronous pipelines.…”

Section: Resultsmentioning

confidence: 99%

Test generation for ultra-high-speed asynchronous pipelines

Shi

Makris

Nowick

et al.

IEEE International Conference on Test, 2005.

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We propose a methodology for testing ultra-high-speed asynchronous pipelines, the latest and most promising asynchronous circuit design style. Unlike traditional delayinsensitive asynchronous micro-pipelines, which use slow capture-pass latches, these circuits employ aggressive handshaking protocols and transparent latches between fine-grain pipeline stages, in order to achieve high performance. Their functional robustness, however, relies on certain timing constraints that need to be satisfied. As a result, these circuits are no longer delay-insensitive, which means that stuck-at faults will not always lead to pipeline stalling. In addition, delay faults may result in violation of these timing constraints, thus affecting not only performance, as in delay-insensitive micro-pipelines, but also functional correctness. To address these new challenges, we develop a test method for both stuck-at and timing constraint violation faults in fine-grain ultra-high-speed asynchronous pipelines. The efficiency of the proposed method is demonstrated on MOUSETRAP, a recently developed pipeline for high-speed applications.

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“…The approach of [13] is based on formal methods and assumes a fault-free reset state. Fault collapsing in sequential circuits is addressed in [14,15]. Checkpoint faults that need to be considered for testing are identified in [14].…”

Section: Introductionmentioning

confidence: 99%

“…Checkpoint faults that need to be considered for testing are identified in [14]. The method in [15] uses equivalence and dominance relations for performing fault collapsing on a restricted set of fault pairs. Only input-output faults of a single gate or flip-flop and branch-stem faults at fanout points are targeted.…”

Section: Introductionmentioning

confidence: 99%

Theorems for efficient identification of indistinguishable fault pairs in synchronous sequential circuits

Amyeen

Pomeranz

Fuchs

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

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We introduce theorems that enable efficient identification of indistinguishable fault pairs in synchronous sequential circuits using an iterative logic array of limited length. These theorems can be used for identifying fault pairs that can be dropped from consideration before diagnostic ATPG starts, thus improving the efficiency of diagnostic ATPG. Experimental results are presented to demonstrate the effectiveness of the proposed theorems, which allow us to identify almost all the indistinguishable fault pairs in finite-state machine benchmarks.

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Single-fault fault collapsing analysis in sequential logic circuits

Cited by 8 publications

References 5 publications

A two-phase fault simulation scheme for sequential circuits

A two-phase fault simulation scheme for sequential circuits

Test generation for ultra-high-speed asynchronous pipelines

Theorems for efficient identification of indistinguishable fault pairs in synchronous sequential circuits

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