Single-Event Upset Cross-Section Trends for D-FFs at the 5- and 7-nm Bulk FinFET Technology Nodes

Xiong, Y.; Pieper, Nicholas J.; Feeley, A.; Narasimham, B.; Ball, D. R.; Bhuva, B. L.

doi:10.1109/tns.2022.3226210

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Single-Event Upset Cross-Section Trends for D-FFs at the 5- and 7-nm Bulk FinFET Technology Nodes

Cited by 5 publications

References 29 publications

An Investigative Study on Performance and Reliability Effects on S2C/TSPC/SCD D-Flip-Flops using 16 nm CMOS Process

An Investigative Study on Performance and Reliability Effects on S2C/TSPC/SCD D-Flip-Flops using 16 nm CMOS Process

Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node

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