Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

Wang, H.-B.; Mahatme, N. N.; Chen, Li; Newton, Michael; Li, Y.-Q.; Liu, R.; Chen, M.; Bhuva, B. L.; Lilja, K.; Wen, Shi-Jie; Wong, Rick; Fung, Rita; Baeg, Sanghyeon

doi:10.1109/tns.2015.2509443

Cited by 18 publications

(11 citation statements)

References 13 publications

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“…For the campaign 170 SEUs were injected in each of the 1233 flip-flops. 57150 of the injected faults showed a (4) rx_eq0.crc32_d64(0) tx_dq0.crc32_d64 (18) rx_eq0.crc32_d8 (15) rx_eq0.crc32_d64(24) tx_dq0.crc32_d64(21) rx_eq0.xgxs_rxd_barrel (7) rx_eq0.xgxs_rxd_barrel (4) tx_dq0.crc32_d64(24) rx_eq0.crc32_d8 (14) Functional Failure Rate…”

Section: Results For Seus In the Sequential Logicmentioning

confidence: 99%

“…The generation of a virtual clock network enables an analysis of the circuit in earlier design stages with regard to clock network issues (such as SETs) and allows the evaluation of different clock network features, such as the fan-out, layout or topology. In fact, recent work has shown that topology and gate load play a significant role in the overall SET sensitivity of clock networks [14].…”

Section: B Virtual Clock Networkmentioning

confidence: 99%

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Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Lange

Glorieux

Alexandrescu

et al. 2019

2019 14th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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With technology scaling, lower supply voltages, and higher operating frequencies clock distribution networks become more and more vulnerable to transients faults. These faults can cause circuit-wide effects and thus, significantly contribute to the functional failure rate of the circuit. This paper proposes a methodology to analyse how the functional behaviour is affected by Single-Event Transients in the clock distribution network. The approach is based on logic-level simulation and thus, only uses the register-transfer level description of a design. Therefore, a fault model is proposed which implements the main effects due to radiation-induced transients in the clock network. This fault model enables the computation of the functional failure rate caused by Single-Event Transients for each individual clock buffer, as well as the complete network. Further, it allows the identification of the most vulnerable flip-flops related to Single-Event Transients in the clock network.The proposed methodology is applied in a practical example and a fault injection campaign is performed. In order to evaluate the impact of Single-Event Transients in clock distribution networks, the obtained functional failure rate is compared to the error rate caused by Single-Event Upsets in the sequential logic.

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Section: Results For Seus In the Sequential Logicmentioning

confidence: 99%

Section: B Virtual Clock Networkmentioning

confidence: 99%

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Lange

Glorieux

Alexandrescu

et al. 2019

2019 14th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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show abstract

“…But, the participation of heavy ions caused the huge size errors in buffered clock tree structure. Wang et al [9] presented and evaluated the two type of clock networks such as clock meshes and the buffered clock tree. They achieved more robustness to SET with the high-protection of buffered clock tree.…”

Section: Related Workmentioning

confidence: 99%

“…• The Single Event Error (SEE) rates were high [9] due to the strong dependence of single event sensitivity.…”

Section: Related Workmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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High-clock skew variations and degradation of driving ability of buffers lead to an additional power dissipation in Clock Distribution Network (CDN) that increases the dimensionality of buffers and coordination among flip-flops. The manual threshold level to predict the Region of Interest (ROI) is not applicable in clustering process due to the complexities of excessive wire length and critical delay. This paper proposes the Distance and Load Weight Updated Clustering (DLWUC) to determine the suitable position of logical components. Initially, the DLWUC utilizes the Hybrid Weighted Distance (HWD) to estimate the distance and construct the distance matrix. The weight value extracted from the sorted distance matrix facilitates the projection of buffers. The updated weight value serves as the base for clustering with labeled outputs. The placement of buffer at the suitable place from load weight updated clustering provides the necessary trade-off between clock provision and load balance. The DLWUC discussed in this paper reduces the size of buffers, skew, power and latency compared to the existing topologies.

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“…When the electronic circuits are operated in radiation environment such as space, the circuits deviate from their expected behaviour leading to malfunction. Single-event transient (SET) is one of the radiation effects [1][2][3][4][5] that causes a transient current spike at the output of the struck device. The effect of such a transient current pulse or spike is that it will propagate through the logic gate circuitry and can be latched in a memory element such as flip-flop (FF) as an erroneous logic state [6].…”

Section: Introductionmentioning

confidence: 99%

Widening and narrowing of time interval due to single‐event transients in 45 nm vernier‐type TDC

Pasupathy

Bindu

2017

IET Circuits, Devices & Syst

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Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in sub-100 nm regime in radiation environment. Time-to-digital converter (TDC) is an important electronic component in many fields such as space applications and is used for measuring time precisely as a digital value. In this study, the effect of SET due to radiation strike on 45 nm vernier-type TDC with a resolution of 7 ps is analysed using cadence spectre circuit simulator. When HI strikes the delay line of TDC close to the START/STOP pulse transition, it either widens or narrows the time interval to be measured, depending on whether it strikes the top/bottom voltage-controlled delay line (VCDL). Results show that the TDC is sensitive if the SET occurs during the transition of START/STOP pulse. Moreover, the change in the time interval occurs in a regular staircase pattern, if the VCDL is struck at all instants near the pulse transition. These errors lead to erroneous digital output and cause abrupt deviations in the staircase transfer characteristics of TDC. SETs in other constituent components of TDC such as D-flip-flop and priority encoder produces glitches which can be mitigated using existing guard gate technique.

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Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

Cited by 18 publications

References 13 publications

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

Widening and narrowing of time interval due to single‐event transients in 45 nm vernier‐type TDC

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