Single Event Transient and TID Study in 28 nm UTBB FDSOI Technology

Li, Rui; Evans, Adrian; Chen, Li; Li, Yuanqing; Glorieux, Maximilien; Wong, Richard; Wen, Shi-Jie; Cunha, J. P. C.; Summerer, Leopold; Ferlet-Cavrois, V.

doi:10.1109/tns.2016.2627015

Cited by 53 publications

(18 citation statements)

References 28 publications

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“…Very recently, [24] designed test elements embedded in a 28 nm UTBB FD-SOI test chip for the purpose of measuring the widths of SETs induced either by heavy ions or laser illumination (1290 nm 1 , 1.5 µm). The authors measured pulses widths in the 300-400 ps range for different laser energies.…”

Section: A Radiation Focused Experimental State-of-the-artmentioning

confidence: 99%

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Dutertre

Beroulle

Candelier

et al. 2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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At first used to emulate the effects of radioactive ionizing particules passing through integrated circuits (ICs), laser illumination is also used to inject faults into the computations of secure ICs for the purpose of retrieving secret data. The CMOS FD-SOI technology is expected to be less sensitive to laser faults injection than the more usual CMOS bulk technology. We report in this work an experimental assessment of the interest of using FD-SOI rather than CMOS bulk to decrease laser sensitivity. Our experiments were conducted on test chips at the 28 nm node for both technologies with laser pulse durations in the picosecond and nanosecond ranges.

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Section: A Radiation Focused Experimental State-of-the-artmentioning

confidence: 99%

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Dutertre

Beroulle

Candelier

et al. 2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…Fully-Depleted-Silicon-On-Insulator (FDSOI) technology has many advantages over conventional bulk ones such as an improvement in the operating frequency, low power consumption, low sensitivity to single event effects (SEE) and short channel effects (SCE) [1]. Several studies have focused on radiation-induced effects on FDSOI devices [2]. Physically, the total ionizing dose (TID) induces a buildup of charges likely to be trapped in the oxide layers of FDSOI transistors, namely the gate oxide, the buried oxide (BOX), and the shallow trench isolation (STI) oxide.…”

Section: Introductionmentioning

confidence: 99%

A new mixed hardening methodology applied to a 28 nm FDSOI 32-bits DSP subjected to gamma radiation

Acuna

Armani

Slimani

et al. 2021

Microelectronics Reliability

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This work presents the performance degradation of a 32-bit DSP fabricated with 28nm FDSOI technology subjected to different levels of gamma radiation. A new mixed hardening methodology based on electrical compensation and thermal regeneration is applied to the irradiated devices to recover the degraded electrical characteristics induced by the total ionizing dose. The application of this new methodology seeks to extend the lifetime of FDSOI integrated circuits under high radiation conditions while keeping good reliability.

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“…However, due to the high working frequency of the FD-SOI circuits, the changeable single event transient (SET) phenomenon is significant in SEE sensitivity evaluation, making radiation hardening design an even more challenging task [18], [22]. The influence of SET in circuits relies on multiple factors, especially for the feature size and technologies, indicating that the existing SET evaluation results for bulk or SOI circuits are hard to be applied to the UTBB FD-SOI circuits [21], [22].…”

Section: Introductionmentioning

confidence: 99%

Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits

Cai

Liu

et al. 2020

IEEE Access

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With device scaling-down, circuits appear more susceptible to transient faults especially for the bulk silicon process. Thus, FD-SOI technology has been widely popular in serious radiation environment due to its high radiation-tolerance inherence created by an additional BOX layer. In this work, seven different inverter chains with two kinds of core voltages, four kinds of channel areas and a stack inverter chain are designed to investigate the SET in advanced 22 nm FD-SOI CMOS technology. A NAND chain is also designed and used for comparison with inverter chains. The sensitivities of diverse SET targets are characterized with different core voltages and heavy-ion tilts. Results showed that the inverter size and the driving current can dominate the occurrence and width distribution of transient pulses. Besides, heavy-ion strike angle, LET, and charge sharing can also affect the pulse width. Though a high LET can deposit adequate energy, the widest pulses are measured in low-LET 84 Kr ion irradiation, rather than in high-LET ions' irradiation, which are attributed to the pulse quenching effect and being investigated by Hspice simulation. The LET dependency and low voltage induced SET widening are all observed in irradiation tests and verified by circuit-level pulse injection. All of the SET sensitive targets are distinguished. The results are highly effective for the designers to suppress and correct the SET-oriented errors to achieve a radiation robust system. INDEX TERMS Fully-depleted silicon-on-insulator (FD-SOI), heavy ions, inverter, single event transient.

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Single Event Transient and TID Study in 28 nm UTBB FDSOI Technology

Cited by 53 publications

References 28 publications

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

A new mixed hardening methodology applied to a 28 nm FDSOI 32-bits DSP subjected to gamma radiation

Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits

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Single Event Transient and TID Study in 28 nm UTBB FDSOI Technology

Cited by 53 publications

References 28 publications

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

A new mixed hardening methodology applied to a 28 nm FDSOI 32-bits DSP subjected to gamma radiation

Characterization of Heavy Ion Induced SET Features in 22-nm FD-SOI Testing Circuits

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A new mixed hardening methodology applied to a 28 nm FDSOI 32-bits DSP subjected to gamma radiation