Single-electron and quantum confinement limits in length-scaled silicon nanowires

Wang, Chen; Jones, Mervyn; Durrani, Z. A. K.

doi:10.1088/0957-4484/26/30/305203

Cited by 13 publications

(12 citation statements)

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“…In the former case, the potential barrier may be associated with additional series QDs, i.e. a multiple tunnel junction (MTJ) system 9 Coulomb diamonds lying between larger diamonds in the electrical characteristics 23 . In Fig.…”

Section: Resultsmentioning

confidence: 99%

Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors

Durrani¹,

Jones²,

Wang³

et al. 2017

Nanotechnology

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Single nanometre scale quantum dots (QDs) have significant potential for many 'beyond CMOS' nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation, <10 nm nanoscale point-contact channels are defined. In this limit of the point-contact approach, ultra-small, few nanometre scale QDs are formed, enabling RT measurement of the full QD characteristics, including excited states to be made. A remarkably large QD electron addition energy ∼0.8 eV, and a quantum confinement energy ∼0.3 eV, are observed, implying a QD only ∼1.6 nm in size. In measurements of 19 RT devices, the extracted QD radius lies within a narrow band, from 0.8 to 2.35 nm, emphasising the single-nanometre scale of the QDs. These results demonstrate that with careful control, 'beyond CMOS' RT QD transistors can be produced using current 'conventional' semiconductor device fabrication techniques.

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Section: Resultsmentioning

confidence: 99%

Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors

Durrani¹,

Jones²,

Wang³

et al. 2017

Nanotechnology

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“…When a semiconductor nanowire with small enough capacitance ( C i ) is coupled to electrodes by insulating tunnel junctions, a single electron nanowire FET could be built (Figure , fourth row; Figure a). − Specifically, the charging energy of one electron to the nanowire is defined by E c = e 2 /2 C i . When the capacitance C i is small enough so that charging energy E c exceeds thermal energy kT , a precise control of the charging of the nanowire channel can be realized to the single electron level.…”

Section: Fundamental Electronic Properties Of Single Nanowire Transis...mentioning

confidence: 99%

Nanowire Electronics: From Nanoscale to Macroscale

et al. 2019

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Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

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“…Correspondingly, the current curves also start to increase rapidly from this conduction band edge position for all bias voltages, which is exactly the evidence of the position of the threshold voltage (V th ). [20] Generally, the highest Fermi energy position in the channel should reach the Fermi level of the source pool at V g = V th , where the energy barrier between the source and the channel should diminish, resulting in the device turning on. The transverse electric field introduced from source and drain voltage has quite limited influence on the highest channel energy level close to the source region, as well as the energy barrier between the channel and the source pool, resulting in the independence of the V th position on V DS voltage.…”

Section: Threshold Characteristics With V Ds Voltage Changingmentioning

confidence: 99%

Observation of source/drain bias-controlled quantum transport spectrum in junctionless silicon nanowire transistor

Guo¹,

Han²,

Zhang³

et al. 2022

Chinese Phys. B

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We investigate the influence of source and drain bias voltages (V DS) on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K. We demonstrate that the transverse electric field introduced from V DS has a minor influence on the threshold voltage of the device. The transverse electric field plays the role of amplifying the gate restriction effect of the channel. The one-dimensional (1D)-band dominated transport is demonstrated to be modulated by V DS in the saturation region and the linear region, with the sub-band energy levels in the channel (E channel) intersecting with Fermi levels of the source (E fS) and the drain (E fD) in turn as V g increases. The turning points from the linear region to the saturation region shift to higher gate voltages with V DS increase because the higher Fermi energy levels of the channel required to meet the situation of E fD = E channel. We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel, equivalent to the effect of thermal temperature on the increase of electron energy. Our work provides a detailed description of the bias-modulated quantum electronic properties, which will give a more comprehensive understanding of transport behavior in nanoscale devices.

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Single-electron and quantum confinement limits in length-scaled silicon nanowires

Cited by 13 publications

References 50 publications

Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors

Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors

Nanowire Electronics: From Nanoscale to Macroscale

Observation of source/drain bias-controlled quantum transport spectrum in junctionless silicon nanowire transistor

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