Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level

Iwasaki, Hiromichi; Naganuma, Jiro; Nitta, Koyo; Nakamura, Ken; Yoshitome, Takeshi; Ogura, Mutsuo; Nakajima, Yasuyuki; Tashiro, Yutaka; Onishi, Takayuki; Ikeda, Mitsuo; Minami, Toshihiro; Endo, Mamoru; Yashima, Yoshiyuki

doi:10.1109/tvlsi.2007.902212

Cited by 4 publications

(3 citation statements)

References 11 publications

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“…The MUX architecture is included in the fabricated singlechip MPEG-2 422P@HL CODEC LSI [8] using 0.13-µm 8-level metal CMOS technology. A micrograph of the LSI is shown in Fig.…”

Section: Implementation and Evaluationmentioning

confidence: 99%

“…Encoder chip interfaces are interconnected with serial cables and MUX is performed in mixture mode as illustrated in Fig. 3 (b), since a super high resolution decoder system is feasibly built up with multiple HDTV decoder LSIs [8]. The overall super high resolution codec is installed in a 1-U (460 × 440 × 44-mm) chassis as illustrated in Fig.…”

Section: Implementation and Evaluationmentioning

confidence: 99%

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A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

Onishi

Nakamura

Yoshitome

et al. 2008

IEICE Transactions on Information and Systems

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SUMMARY This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.

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“…The MUX architecture is included in the fabricated singlechip MPEG-2 422P@HL CODEC LSI [8] using 0.13-µm 8-level metal CMOS technology. A micrograph of the LSI is shown in Fig.…”

Section: Implementation and Evaluationmentioning

confidence: 99%

Section: Implementation and Evaluationmentioning

confidence: 99%

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

Onishi

Nakamura

Yoshitome

et al. 2008

IEICE Transactions on Information and Systems

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show abstract

“…Therefore, we have developed a professional H.264/AVC video encoder LSI, SARA/E, that can be configured with multi-chip for HDTV, and that has 257GOPS ME/MC engines with wide search ranges and 72Mbit eDRAMs for bandwidth reductions. It is the successor to our previous MPEG-2 422P@HL CODEC chip (VASA) [6]. Fig.…”

Section: Introductionmentioning

confidence: 96%

An H.264/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures

Nitta

Ikeda

Iwasaki

et al. 2008

2008 IEEE Symposium on VLSI Circuits

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An H.264/AVC encoder LSI (named SARA/E) that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains 257GOPS motion estimation and compensation (ME/MC) engines with search ranges of -271.75 to +199.75 (H) / -109.75 to +145.75 (V), which can utilize almost all H.264/AVC ME/MC tools, multiple reference frame, variable block size, 1/4-pel prediction, macroblock adaptive field/frame prediction, temporal/spatial direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2 to 1.7dB higher than the JM. It was successfully fabricated in a 90nm 9level metal CMOS technology. It integrates 140 million transistors.

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Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4:2:2 H.264/AVC encoder LSI

Onishi

Sano

Nitta

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level

Cited by 4 publications

References 11 publications

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

An H.264/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures

Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4:2:2 H.264/AVC encoder LSI

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