Simultaneously performing interlayer copper interconnecting and TSV filling in stacked chips at room temperature based on copper electroplating

Abstract

In this work, we have developed a novel method for simultaneously performing interlayer copper interconnecting and Cu filling inside TSVs. It was applied to demonstrate two-layer stacked chips that process the development of interlayer copper interconnecting and Cu pillar filling in through-silicon vias (TSVs) by copper electroplating at room temperature (25 °C). In the two-layer stacked structure, a chip with TSVs was bonded with another chip without TSVs using a permanent bonding adhesive. After all micro-channels were immersed in the copper sulfate electroplating solution by vacuum pumping, copper electroplating made the interlayer copper interconnecting structures and the simultaneously filled copper pillars in TSVs a homogeneous three-dimensional (3D) interconnected structure and did not show original interfaces. Furthermore, no apparent gaps, air bubbles, or cracks were observed in the 3D copper interconnecting structure. The measured direct current resistance and the critical frequency at which the skin effect occurs of the formed 3D copper interconnected structure were very close to the theoretical value. The pure copper 3D interconnected structure without inner interfaces is very valuable for high-quality 3D integrated systems.