Simultaneous Switching Noise of CMOS Devices and Systems

Senthinathan, R.; Prince, J.L.

doi:10.1007/978-1-4615-3204-0

Cited by 122 publications

(35 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recently, several approaches have been proposed for power supply noise [10][1] [2] and maximum instantaneous current [8] [9][13] [7][6] estimation. Senthinathan and Prince [10] derived several closed-form equations to calculate simultaneous switching noise (SSN).…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Estimation of maximum power supply noise for deep sub-micron designs

Jiang

Cheng

Deng

1998

Proceedings of the 1998 International Symposium on Low Power Electronics and Design - ISLPED '98

View full text Add to dashboard Cite

We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and other input characteristics as parameters. Based on the cells' current and voltage libraries, the power supply noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high power supply noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum power supply noise.

show abstract

Section: Related Workmentioning

confidence: 99%

“…Senthinathan and Prince [10] derived several closed-form equations to calculate simultaneous switching noise (SSN). Chang et al [1] proposed a scaling model to estimate the ground bounce caused by the switching in internal circuitry for deep sub-micron circuits.…”

Section: Related Workmentioning

confidence: 99%

Estimation of maximum power supply noise for deep sub-micron designs

Jiang

Cheng

Deng

1998

Proceedings of the 1998 International Symposium on Low Power Electronics and Design - ISLPED '98

View full text Add to dashboard Cite

show abstract

“…With the progress of modern CMOS technology, especially the increase in clock frequency and pulse edge rate, and the decrease in power supply voltage and noise margin, the power/ground noise creates significant and new challenges for electromagnetic interference/electromagnetic compatibility (EMI/EMC) and packaging engineers. Simultaneous switching noise (SSN) has become one of the major concerns [1], [2]. This type of electromagnetic disturbance (noise), also known as delta-I noise or power/ground plane bounce, has been discussed intensively over the last decade and different approaches have been used to maintain a noise-free PDS.…”

Section: Introductionmentioning

confidence: 99%

Novel Planar Electromagnetic Bandgap Structures for Mitigation of Switching Noise and EMI Reduction in High-Speed Circuits

Qin

Ramahi

Granatstein

2007

IEEE Trans. Electromagn. Compat.

View full text Add to dashboard Cite

Abstract-Planar electromagnetic bandgap (EBG) structures with novel meandered lines and super cell configuration are proposed for mitigating simultaneous switching noise propagation in high-speed printed circuit boards. An ultrawide bandgap extending from 250 MHz to 12 GHz and beyond is demonstrated by both simulation and measurement, and a good agreement is observed. These perforated EBG-based power planes may cause spurious and unwanted radiation. In this paper, leakage radiation through these imperfect planes is carefully investigated. It is found that the leakage field from these planar EBG structures is highly concentrated around the feed point, and the field intensity is attenuated dramatically when passing across several periods of patches. A novel concept of using these EBG structures for electromagnetic interference reduction is also introduced. Finally, the impact of power plane with EBG-patterned structures on signal integrity is studied. Index Terms-Electromagnetic bandgap (EBG), electromagnetic interference (EMI), signal integrity (SI), simultaneous switching noise (SSN).

show abstract

“…H IGH-FREQUENCY noise in printed circuit boards (PCBs) results from both simultaneous switching of digital logic within the core, as well as simultaneous switching of device I/O, often referred to as simultaneous switching noise (SSN) and SSO [1]. This high-frequency noise on the dc power bus in PCBs can lead to signal integrity (SI) and electromagnetic interference (EMI) problems.…”

Section: Introductionmentioning

confidence: 99%

“…Finally, dc power bus design implications are discussed in Section VI. TO LOCAL DECOUPLING Local decoupling capacitors, i.e., SMT decoupling capacitors placed adjacent to the power/ground pins of IC devices, (1) can be beneficial in mitigating high-frequency power bus noise. Local decoupling capacitors can be effective up to the gigahertz range.…”

Section: Introductionmentioning

confidence: 99%

Estimating the noise mitigation effect of local decoupling in printed circuit boards

Fan

Cui

Drewniak

et al. 2002

IEEE Trans. Adv. Packag.

View full text Add to dashboard Cite

Abstract-Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bus noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling.Index Terms-Closed-form expressions for via inductances, estimation of power-bus noise reduction due to local decoupling, local decoupling, mutual inductance, printed circuit board layer stackup, shared-via decoupling.

show abstract

Simultaneous Switching Noise of CMOS Devices and Systems

Cited by 122 publications

References 0 publications

Estimation of maximum power supply noise for deep sub-micron designs

Estimation of maximum power supply noise for deep sub-micron designs

Novel Planar Electromagnetic Bandgap Structures for Mitigation of Switching Noise and EMI Reduction in High-Speed Circuits

Estimating the noise mitigation effect of local decoupling in printed circuit boards

Contact Info

Product

Resources

About