Simultaneous scheduling, allocation and binding in high level synthesis

Kollig, P.; Al-Hashimi, Bashir M.

doi:10.1049/el:19971039

Cited by 29 publications

(17 citation statements)

References 6 publications

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“…The second group tries to address the global optimality and performs simultaneous functional unit and register binding. Representative algorithms include simulated annealing [7][8] [18], simulated evolution [21], and ILP (integer linear programming) [13] [26]. Since the subtasks of high-level synthesis are highly interrelated, simultaneous optimization approaches try to consider all the involved optimization parameters together and explore the combined solution space for overall better results.…”

Section: Related Workmentioning

confidence: 99%

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Chen

Cong

Fan

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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Section: Related Workmentioning

confidence: 99%

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Chen

Cong

Fan

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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“…The first group performs simultaneous functional unit and register binding. Representative algorithms include simulated annealing [5,9,24], simulated evolution [29], and integer linear programming (ILP) [13,35]. Since the subtasks of behavioral synthesis are highly interrelated, simultaneous optimization approaches try to consider all the involved optimization parameters together for globally better results.…”

Section: Related Workmentioning

confidence: 99%

Platform-based resource binding using a distributed register-file microarchitecture

Cong¹,

Fan²

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.

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“…The behavioral description of the 32 point DCT is synthesized using the ARGEN high-level synthesis system [13]. The output of the high-level synthesis system are functional control and functional structural RTL data path.…”

Section: Automated Design Space Explorationmentioning

confidence: 99%