Simultaneous optimization for low dropout regulator and its error amplifier with process variation

Abstract

Due to its low power, small ripple and low noise properties, low-dropout regulators (LDO) are often used in on-chip applications. However, there are few design automation works focusing on this important circuit. In this paper, an automatic optimization process is proposed to generate the optimal sizing of low dropout regulators. The devices in the LDO circuit and its error amplifier are both considered in the optimization process for reducing the overall circuit cost. The process variation effects are also considered in this work to guarantee the circuit performance after manufactured. As demonstrated in the experiments, the proposed approach successfully solves the unreachable specification in previous work and significantly improves the design yield of the generated circuits.