Simultaneous module selection and scheduling for power-constrained testing of core based systems

Abstract

We address the problem of power-constrained testing of core based system chips. Built-in self-test methodology for testing individual cores is assumed, and sharing of test resources (pattern generators and signature registers) among cores is permitted. We consider a scenario where the system integrator is dealing with "soft" or "firm cores" for which the final realization has not been frozen and the flexibility of module selection rests with the integrator. We argue that advantage can be taken of this flexibility in coming up with a power-constrained test plan. Since scheduling of test sessions also affects power dissipation in a crucial way, we present an algorithm for simultaneous module selection and test scheduling. Our objective is to minimize the test application time treating the test area overhead and total power dissipation as constraints. We report thye results of our implementation of a test planner on two examples.

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

“…The solution for this particular ILP is X T CS 1 = 1, X T CS 14 = 1 and X T CS 15 The following information is necessary for performing a thermal simulation for a test session: the chip floorplan, the test power values for the cores in the test session, and the corresponding test lengths. The thermal simulator produces temperature traces for each core for the entire duration of the test session, based on a user specified time step.…”

“…The common idea behind PCTS is to impose a chip-wide maximum allowable limit on power consumption, which should not be exceeded during test application. Several recently proposed powerconstrained test scheduling algorithms aim to maximise the number of tests running in parallel without exceeding this limit [2,9,11,7,6,1,15,12,13].…”

“…While there still are unscheduled cores, the algorithm tries to assign them to the current test session TS. The test session TS is initially empty (line 11) and cores are added to it until no core can be added due to resource conflicts (lines [12][13][14][15][16][17][18][19][20][21][22]. A thermal simulation is performed on TS to verify if it complies with Tmax .…”

“…Techniques falling in the first category include low-power scan chain architectures with gated clocks [18,17], scan cell and test pattern reordering [3,5], and low-transition test patterns generated by specialised ATPG algorithms [22] and low-transition TPGs [21]. The second category of techniques is mainly based on powerconstrained test scheduling algorithms [2,9,11,7,6,1,15,12,13] 1 . This paper focuses on avoiding overheating during test through appropriate test scheduling.…”

Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling

“…Techniques falling in the first category include low-power scan chain architectures with gated clocks [16,4,14], scan cell and test pattern reordering [3,5], and low-transition test patterns generated by specialized ATPG algorithms [19] and low-transition TPGs [18]. The second category of techniques is mainly based on power-constrained test scheduling algorithms [2,8,10,7,6,1,13,11,12] and the recently proposed thermal-safe test scheduling algorithms [15]. Unlike power-constrained test scheduling approaches, the thermal-safe test scheduling method we have presented in [15] guarantees hot-spotfree test schedules by ensuring that a given critical die temperature is not exceeded during test.…”