Simulations of Ultralow-Power Nonvolatile Cells for Random-Access Memory

Abstract

Dynamic random-access memory (DRAM), which represents 99% of random access memory (RAM), is fast and has excellent endurance, but suffers from disadvantages such as short data retention time (volatility) and loss of data during readout (destructive read). As a consequence, it requires persistent data refreshing, increasing energy consumption, degrading performance and limiting scaling capacity. It is therefore desirable that the next generation of RAM will be non-volatile (NVRAM), low power, high endurance, fast and nondestructively read. Here, we report on a new form of NVRAM: a compound-semiconductor charge-storage memory that exploits quantum phenomena for its operational advantages. Simulations show that the device is extremely low power, with 100 times lower switching energy per unit area than DRAM, but with similar operating speeds. Non-volatility is achieved due to the extraordinary band offsets of InAs and AlSb, providing a large energy barrier (2.1 eV) which prevents the escape of electrons. Based on the simulation results, an NVRAM architecture is proposed for which extremely low disturb-rates are predicted as a result of the quantum-mechanical resonant-tunneling mechanism used to write and erase.

ULTRARAM: Toward the Development of a III–V Semiconductor, Nonvolatile, Random Access Memory

“…These characteristics are predicted by simulations of quantum transport [5] and have previously been demonstrated in single devices at room temperature [6]. The intricate physics of the tunneling mechanism used here and a comparison of ULTRARAM with current and emerging memory technologies are described in detail in our previous work for the interested reader [5]. Additionally, the devices out-perform other resonant-tunneling-based memories in endurance benchmarks with at least a similar logic retention time [7], [8].…”

“…This resolves the paradox of universal memory, as the tunneling structure provides a high-energy barrier when there is no bias applied, but allows resonanttunneling (i.e., transparent barriers) at program/erase (P/E) voltages of around 2.5 V, approximately ten times lower than flash. These characteristics are predicted by simulations of quantum transport [5] and have previously been demonstrated in single devices at room temperature [6]. The intricate physics of the tunneling mechanism used here and a comparison of ULTRARAM with current and emerging memory technologies are described in detail in our previous work for the interested reader [5].…”

“…Moreover, CG-D resistance is improved from 10 3 to >10 10 (the limit of measurement). Within the array, architecture S-D current (I S−D ) is measured via the BG terminal as the D terminals are buried within the random access memory (RAM) architecture [5], as shown in Fig. 1.…”

“…The other cell on the array which shares this BL is undisturbed as its CG terminal is floating. Previously, a halfvoltage architecture was proposed in which individual memory cells are selected by applying half of the required P/E voltage to the WL and the other half to the BL [5]. It is found that the same 0/1 contrast can be obtained using this P/E scheme, whereby ±1.25 V pulses applied to BL and WL are used to cycle the memory state.…”

“…Additionally, the devices out-perform other resonant-tunneling-based memories in endurance benchmarks with at least a similar logic retention time [7], [8]. Most importantly, the FG design allows for high-density array architectures and the possibility of vastly improved readout (1/0) contrast [5]. Moreover, the current through the gate during P/E cycles is extremely small, significantly reducing memory power consumption by comparison.…”