Simulation study of various factors affecting the performance of vertical organic field-effect transistors

Abstract

Vertical organic field-effect transistors (VOFETs) can offer a short channel architecture that can further enhance the performance at low operating voltages, which makes it more viable for organic electronics applications. VOFETs can be prepared using low-cost techniques that reduce the high processing costs and can operate at high current densities and relatively high frequencies. To further improve the performance, high current density, and operating frequency, the physics of charge carrier transport should be understood well with the simulation. The main problem with VOFET is the high off-current which is inevitable due to conduction from the source to the drain contact. Many efforts have been made to reduce the off-state current by the addition of an insulating layer on top of the source electrode, which further increases the processing complexity and cost of fabrication. Simulations based on device geometry, contact barriers, and organic semiconductor parameters are carried out to study the charge carrier transport in VOFET. The simulation results show that the most important factor, to enhance the performance is the device geometry or architecture, which requires a specific fill factor, a ratio of the exposed gate dielectric width to the total width of the device with the source electrode. The simulation results also show a different type of working physics of the basic VOFET architecture where the On/Off ratio and subthreshold swing are largely dependent on the initial negative gate field instead of the accumulated charge carriers at positive gate fields. Optimized VOFET architecture is then simulated for variation in contact barrier and semiconductor properties, which show further enhancement in performance.

Predicting the miniaturization limit of vertical organic field effect transistor (VOFET) with perforated graphene as a source electrode

“…The transfer characteristics of the VOFET show that the increase in perforation size/gate width results in the lowering of the leakage current from source to drain. This is attributed to the fact that at high values of gate width/perforation width, the negative gate field blocks the charge carrier flow from source to drain [38]. A dielectric coating on top of the source electrode can further minimize the leakage current and a few reports are available on this but will add up the extra cost and processing time to the device fabrication [39].…”