Simulation Differences Between Academia and Industry: A Branch Prediction Case Study

Loh, Gabriel H.

doi:10.1109/ispass.2005.1430556

Cited by 8 publications

(6 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We have also undertaken similar simulations with neural predictors [6,15] and in addition to the SPEC benchmarks we have used the Championship Branch Prediction benchmarks [7,16]. However, due to space limitations we have not shown the results of these simulations in this paper.…”

Section: Simulationsmentioning

confidence: 99%

Understanding Prediction Limits Through Unbiased Branches

Vintan

Gellért

Florea

et al. 2006

Advances in Computer Systems Architecture

View full text Add to dashboard Cite

The majority of currently available branch predictors base their prediction accuracy on the previous k branch outcomes. Such predictors sustain high prediction accuracy but they do not consider the impact of unbiased branches which are difficult-to-predict. In this paper, we quantify and evaluate the impact of unbiased branches and show that any gain in prediction accuracy is proportional to the frequency of unbiased branches. By using the SPECcpu2000 integer benchmarks we show that there are a significant proportion of unbiased branches which severely impact on prediction accuracy (averaging between 6% and 24% depending on the prediction context used).

show abstract

Section: Simulationsmentioning

confidence: 99%

Understanding Prediction Limits Through Unbiased Branches

Vintan

Gellért

Florea

et al. 2006

Advances in Computer Systems Architecture

View full text Add to dashboard Cite

show abstract

“…The prediction in this algorithm using the outcome of a 4 most recent branches with 2-bits from the branch address to compose a 6-bit which is the index to one of the 64 counters from the PHT. Also there exists another type of the two-level predictor, which is known as the Local History two-level predictor [17][18][19] shown in Figure 3. Figure 2.…”

Section:  Issn: 2088-8708mentioning

confidence: 99%

Hybrid branch prediction for pipelined MIPS processor

Al-Khalid

Omran

2020

IJECE

View full text Add to dashboard Cite

In the modern microprocessors that designed with pipeline stages, the performance of these types of processors will be affected when executing branch instructions, because in this case there will be stalls in the pipeline. In turn this causes in reducing the Cycle Per Instruction (CPI) of the processor. In the case of executing a branch instruction, the processor needs an extra clocks to know if that branch will happen (Taken) or not (Not Taken) and also it requires calculating the new address in the case of the branch is Taken. The prediction that the branch is T / NT is an important stage in enhancing the processor performance. In this research more than one method of branch prediction (hybrid) is used and the designed circuit will choose different types of prediction algoritms depending on the type of the branch. Some of these methods were used are static while the other are dynamic. All circuits were built practically and examined by applying different programs on the designed predictor algorithm to compute the performance of the processor.

show abstract

“…The lack of detailed information about BPs in real processors and subsequent differences in the simulation frameworks used in academia and industry may threaten the validity of BP studies. To address this, a closer collaboration between academia and industry is required.…”

Section: Conclusion and Future Outlookmentioning

confidence: 99%

A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

View full text Add to dashboard Cite

Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers. KEYWORDSdynamic branch predictor, hybrid BP, neural BP, perceptron predictorside BP, pipelining, predictor accuracy, review, side BP, speculative execution, two-level BP INTRODUCTIONControl-changing instructions such as branches add uncertainty in the execution of dependent instructions and thus lead to large performance loss in pipelined processors. To offset their overhead, accurate prediction of branch outcomes is vital. Since branch misprediction incurs high latency (eg, 14 to 25 cycles 1 ) and wastes energy due to execution of instructions on wrong-path, an improvement in BP* accuracy can boost performance and energy efficiency significantly. For example, experiments on real processors showed that reducing the branch mispredictions by half improved the processor performance by 13%. 2Effective design and management of BPs, however, presents several challenges. Design of BP involves a strict tradeoff between area, energy, accuracy, and latency. An increase in BP complexity for improving accuracy may make it infeasible for implementation or offset its performance benefit. For example, a 512 KB perceptron predictor may provide lower instruction-per-cycle than its 32 KB version, 3 and a 2-cycle fully accurate BP may provide lower instruction-per-cycle than a 1-cycle partially inaccurate BP. 4 Further, due to its high access frequency, BP becomes a thermal hot-spot, 5 and hence, reducing its dynamic and leakage energy is important. Clearly, intelligent techniques are required for resolving these issues.Further, recently, researchers have demonstrated two security vulnerabilities viz., "Meltdown" and "Spectre," which exploit speculative execution feature of modern CPUs. 6-8 For example, Spectre vulnerability works on the observation that the speculative execution due to a branch misprediction may leave side effects, which can reveal sensitive data to attackers, eg, if the memory accesses performed during speculative execution depends on sensitive data, the resulting state of the cache forms a side-channel through which the sensitive data can be leaked. These vulnerabilities affect nearly every modern CPU. While avoiding speculative execution (eg, disabling branch prediction) can mitigate these vulnerabilities, it leads to significant performance loss. In light of these vulnerabilities and associated tradeoffs, a deeper study of branch predictors is definitely required. Contributions:In this ...

show abstract

Simulation Differences Between Academia and Industry: A Branch Prediction Case Study

Cited by 8 publications

References 33 publications

Understanding Prediction Limits Through Unbiased Branches

Understanding Prediction Limits Through Unbiased Branches

Hybrid branch prediction for pipelined MIPS processor

A survey of techniques for dynamic branch prediction

Contact Info

Product

Resources

About