Simulation based system level fault insertion using co-verification tools

Eklow, B.; Hosseini, Ahmad; Khuong, Chi; Pullela, S.; Vo, Toai; Chau, Henry Hoi Ki.

doi:10.1109/test.2004.1387332

Cited by 17 publications

(13 citation statements)

References 3 publications

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“…Despite the benefits offered by the above techniques, individual component testing and interconnection testing are no longer sufficient to guarantee the quality of complex circuit boards [19,20]. It is often the case that all the chips on a board pass ATE tests, but the board still fails functional test, a scenario referred to as "No Trouble found" (NTF).…”

Section: Compared To Detection Isolation Is a More Difficult Task Inmentioning

confidence: 99%

“…If such data is not available in sufficient quantity, faultinsertion test (FIT) can be used to extract fail data in an artificial manner [20,43].…”

Section: Automated Diagnosis Systemmentioning

confidence: 99%

“…Knowledge acquisition is the major bottleneck for developing a usable diagnosis engine. In contrast, rule-based and model-based techniques [20,27] can assist in the initial creation of the knowledge base, but the acquisition of such knowledge requires a technician's expertise and the knowledge may be biased or flawed if the board structure is not fully understood.…”

Section: Problem Statement and Chapter Contributionsmentioning

confidence: 99%

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Knowledge-Driven Board-Level Functional Fault Diagnosis

Zhang

Chakrabarty

et al. 2017

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The semiconductor industry continues to relentlessly advance silicon technology scaling into the deep-submicron (DSM) era. High integration levels and structured design methods enable complex systems that can be manufactured in high volume.However, due to increasing integration densities and high operating speeds, subtle manifestation of defects leads to functional failures at the board level. Functional fault diagnosis is, therefore, necessary for board-level product qualification. However, ambiguous diagnosis results can lead to long debug times and wrong repair actions, which significantly increase repair cost and adversely impact yield.

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Section: Compared To Detection Isolation Is a More Difficult Task Inmentioning

confidence: 99%

“…If such data is not available in sufficient quantity, faultinsertion test (FIT) can be used to extract fail data in an artificial manner [20,43].…”

Section: Automated Diagnosis Systemmentioning

confidence: 99%

Section: Problem Statement and Chapter Contributionsmentioning

confidence: 99%

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Knowledge-Driven Board-Level Functional Fault Diagnosis

Zhang

Chakrabarty

et al. 2017

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show abstract

“…Hardware fault-insertion test (FIT) is a technique that intentionally inserts wrong values at pin/logic level to model the effects of manufacturing defects and in-field intermittent and transient errors [7], [8]. FIT is an essential tool to verify the robustness and error-handling capabilities of boards and systems and it is an accurate and objective method to verify the ability of diagnostics to accurately detect and diagnose failures at a board or system level [8].…”

Section: Fault-insertion Testmentioning

confidence: 99%

“…FIT is an essential tool to verify the robustness and error-handling capabilities of boards and systems and it is an accurate and objective method to verify the ability of diagnostics to accurately detect and diagnose failures at a board or system level [8]. FIT is a required system test step at companies such as Cisco Systems, Inc. because it is the only method that allows system hardware, integrated with system software, to be tested as a whole in the area of hardware-error handling.…”

Section: Fault-insertion Testmentioning

confidence: 99%