Simulation based study of wireless RF interconnects for practical CMOs implementation

More, Ankit; Taşkın, Barış

doi:10.1145/1811100.1811111

Cited by 6 publications

(3 citation statements)

References 7 publications

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“…This technology realized parallel transmission between multi-band electromagnetic wave by using highfrequency generator and high precision filter. More [8] researched several parameters on wireless RF technology such as wavelength and noise through simulations. Zhao [9] proposed WNoC based on Ultra Wide Band Radio (UWB), whose delivery frequency is just tens GHz.…”

Section: Relative Workmentioning

confidence: 99%

An Exploration on Quantity and Layout of Wireless Nodes for Hybrid Wireless Network-on-Chip

Yuan

Chen

et al. 2014

2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security

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As the scaling of integration, massive remote communication has become the main bottleneck of system performance for network-on-chip (NoC). Most packets have to travel long distances from source to destination, leading to long latency and severe contention. Hybrid Wireless NoC(HWiNoC) has emerged as a popular method to handle remote transmission in NoC, in which packets can be modulated to wireless channel and delivered to remote nodes in just one hop. However wireless nodes introduces non-trivial overhead. In this paper, we explore the quantity and layout of wireless nodes in HwiNoC. We first define three optimization rules, with the main optimization targets being minimizing Maximum Distance(MD), Average Distance(AD) and Sum of Distance from each nodes to wireless nodes(SD) respectively. We further decide the optimal wireless count to ensure the maximum performance gain per wireless node, and propose a novel heuristic to find a near optimal target layout. Experiment results show that minimizing AD and SD outperforms minimizing MD by 6.21% and 8.19% in terms of average packet latency under synthetic traffic patterns, while minimizing AD exhibits more stability than the other two rules. And our heuristic layout introduces less than 1% performance loss in terms of AD and SD compared with the enumerated optimal layout, while the calculate complexity is reduced from O(N!) to O(N).

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Section: Relative Workmentioning

confidence: 99%

An Exploration on Quantity and Layout of Wireless Nodes for Hybrid Wireless Network-on-Chip

Yuan

Chen

et al. 2014

2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security

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“…Therefore, some strategies should be made to distribute transceivers/receivers inside the integrated circuit such that they can be used efficiently. Moreover, feasibility of managing the interferences between the wires (or external sources) and RF-interconnects is approved in [16] by considering some design considerations such as CDMA and CFDMA coding.…”

Section: On-chip Rf-interconnectsmentioning

confidence: 99%

“…It is also shown that it's better to use a combination of TSVs and RF-Is due to the area and power overheads of RF resources. Authors of [16] have presented some design considerations making the use of RF-Is possible on a die by minimizing the undesired electromagnetic signal coupling and interference between on-chip antennas and on-chip antennas and metal interconnects.…”

Section: Introductionmentioning

confidence: 99%

RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion

Pourshirazi

Jahanian

2012

2012 15th Euromicro Conference on Digital System Design

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RF/wireless interconnect is an emerging technology for mitigating the problems of nano-scale metal wires in ultralarge integrated circuits. However, there is no EDA physical design flow for using this technology in conventional application specific ICs. In this paper, an architecture containing both wired and wireless interconnects is presented for regular ASICs corresponding with assignment and placement algorithms for RF-interconnect resources. Experimental results show that total wirelength (routing congestion) and critical delay of attempted benchmarks is reduced by 16.8% and 30.1% on average, respectively. These benefits are earned in the cost of 2.33% area and 11.89% power consumption overhead for large circuits. Moreover, paper concludes that the area and power consumption overheads are lower considerably when the size of design grows.

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EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs

Taşkın

2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

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Simulation based study of wireless RF interconnects for practical CMOs implementation

Cited by 6 publications

References 7 publications

An Exploration on Quantity and Layout of Wireless Nodes for Hybrid Wireless Network-on-Chip

An Exploration on Quantity and Layout of Wireless Nodes for Hybrid Wireless Network-on-Chip

RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion

EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs

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