Simulation-based Defect Printability Analysis on Alternating Phase Shifting Masks for 193nm Lithography

Pang, Liang; Yu, Zongchang; Luk-Pat, Gerard; Chen, Jerry X.; Volk, William Waters

doi:10.1117/12.468205

Cited by 5 publications

(2 citation statements)

References 1 publication

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“…Numerical Technology pioneered this field with the i-Virtual Stepper System™. [74][75][76][77][78][79][80][81][82][83] (later acquired by Synopsys, also led by the author). The Applied Materials AERA™ inspection system is an aerial-image-based mask-inspection system.…”

Section: Curvilinear Mask Inspectionmentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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Section: Curvilinear Mask Inspectionmentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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“…However, due to the number of real defects detected during inspection and the throughput limitations of the AIMS tool, it may be impractical and is probably unnecessary to disposition every defect on the AIMS tool. Instead, an aerial-image based simulator could be used upstream after inspection, thereby lithographically filtering the bulk of the sub-specification defects, including inspection false defects or artifacts, leaving only marginal and lithographically significant defects for further AIMS disposition and repair [17][18][19][20][21]. This requires a fast and accurate aerial image simulation from inspection images and an automated defect classification-based aerial image to be developed.…”

Section: Introductionmentioning

confidence: 99%

From Computational Lithography to Computational Inspection: Inverse Lithography Technology (ILT) and Inverse Inspection Technology (IIT)

Pang¹,

Peng²,

et al. 2010

ECS Trans.

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For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.

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A study of defect measurement techniques and corresponding effects on the lithographic process window for a 193-nm EPSM photomask

et al. 2003

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Simulation-based Defect Printability Analysis on Alternating Phase Shifting Masks for 193nm Lithography

Cited by 5 publications

References 1 publication

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Inverse lithography technology: 30 years from concept to practical, full-chip reality

From Computational Lithography to Computational Inspection: Inverse Lithography Technology (ILT) and Inverse Inspection Technology (IIT)

A study of defect measurement techniques and corresponding effects on the lithographic process window for a 193-nm EPSM photomask

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