Simulation and experimental study of 3-step junction termination extension for high-voltage 4H-SiC gate turn-off thyristors

Lin, Lei; Zhao, J.H.

doi:10.1016/j.sse.2013.04.029

Cited by 19 publications

(8 citation statements)

References 15 publications

(15 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Silicon carbide (SiC) has recently gained a great attention as a wide band-gap semiconductor to be used in high-fRequency high-power applications requiring high-temperature operation and/or high radiation-damage resistance. [1][2][3][4][5] The excellent electronic properties in terms of breakdown electric field strength, thermal conductivity, and relatively high electron mobility make SiC attractive for fabrication of power devices with die-sizes and reduced power losses. 6) In this context, SiC-based Schottky contacts have been extensively proposed for understanding the material physics and to lead the design of new devices for harsh-environments.…”

Section: Introductionmentioning

confidence: 99%

Simulation and analysis of the current–voltage–temperature characteristics of Al/Ti/4H-SiC Schottky barrier diodes

Zeghdar

Dehimi

Pezzimenti

et al. 2019

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

The current-voltage characteristics of Al/Ti/4H-SiC Schottky barrier diodes have been investigated in the 85-445 K temperature range by means of a combined numerical and analytical simulation study. Simulation results showed a good agreement with measurements in the whole explored current range from 10 μA to 10 mA. The main device electrical parameters, namely the barrier height (BH) and ideality factor, were found to be strongly temperature-dependent. In particular, the ideality factor decreases while the BH increases with increasing temperature. The observed behaviours have been successfully interpreted by using the thermionic emission theory with a triple Gaussian distribution of the BH in three different temperature ranges, i.e. 85 ⩽ ΔT 1 ⩽ 135 K, 180 ⩽ ΔT 2 ⩽ 270 K, and 315 ⩽ ΔT 3 ⩽ 445 K. The corresponding Richardson constants areand A 3 * = 173.21 A cm −2 K −2 , respectively. These values are close to the theoretical result of 146 A cm −2 K −2 expected for n-type 4H-SiC. Finally, it has been highlighted that the current flowing through the Schottky junction is also determined by the thermionic-field emission mechanism.

show abstract

Section: Introductionmentioning

confidence: 99%

Simulation and analysis of the current–voltage–temperature characteristics of Al/Ti/4H-SiC Schottky barrier diodes

Zeghdar

Dehimi

Pezzimenti

et al. 2019

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…Therefore, alternative methods of forming p-type regions in GaN are needed, which includes selective p-GaN regrowth [20], Mg implantation in unintentionally doped GaN [21,22] and n-type GaN [23,24], and counter-doping using n-type implantation to partially compensate the acceptors in the p + layer [25]. The first technique involves complex fabrication process while the latter two require an ion implantation and high temperature annealing process, where the activation of implanted dopants may vary with the annealing conditions and additionally create defects, which compromise the device performance [26][27][28]. In order to circumvent these challenges, implantation-free techniques such as etch termination can be employed.…”

Section: Introductionmentioning

confidence: 99%

“…Hence in this work, viable implantation-free edge termination techniques suitable for GaN, such as simple field plate (FP), single-and multi-etch JTE, and a hybrid FP-JTE structure are proposed for the first time. These implantation-free structures are advantageous due to their simple design and processing, and high termination effectivity [26]. Such techniques have also been proven beneficial in Si and SiC technologies [27][28][29][30][31].…”

Section: Introductionmentioning

confidence: 99%

Implantation-free edge termination structures in vertical GaN power diodes

Shurrab

Singh

2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

Gallium nitride (GaN) is a promising candidate for power applications, due to its superior electrical properties such as high critical breakdown field and saturation drift velocity. The recent emergence of GaN substrates with low defect densities has made it feasible to develop efficient vertical GaN power diodes. However, the breakdown voltage of these diodes is far from the theoretical value, due to the lack of suitable edge termination techniques in GaN such as junction termination extension (JTE). This is attributed to the processing challenges in fabricating GaN power diodes where it is difficult to form p-type regions through implantation. This work addresses this challenge and proposes the design, optimization, and a comprehensive design methodology for implantation-free, edge termination techniques such as field plate (FP), single and multi-etch JTE, and a hybrid FP-JTE structure, suitable for vertical GaN diodes. The proposed approaches demonstrate that close to theoretical breakdown voltages (>80%) are achievable, with greater area efficiency, simple processing, and high tolerance in process variation.

show abstract

“…It is especially important when it comes to designing high voltage devices on SiC because the material cost is much more expensive than the conventional silicon wafer. The most widely used efficient edge termination techniques for SiC devices are floating field rings (FFRs), junction termination extension (JTE) [1], [2], and multi-step etched JTE [3], [4]. When using FFRs, a narrow definition of the space between rings, and tight control of defects are required in order to attain the designed breakdown voltage.…”

Section: Introductionmentioning

confidence: 99%

“…When using FFRs, a narrow definition of the space between rings, and tight control of defects are required in order to attain the designed breakdown voltage. Blocking performance with JTE-based edge termination is sensitive to the impurity dose, and requires multiple-zone for ultrahigh voltage ratings (∼10kV) formed by multiple processing steps [3], [4]. Above all, both FFRs, and JTE waste large amount of space on the edge of chips, because they are more than 3 times wider than the drift layer thickness as a rule of thumb.…”

Section: Introductionmentioning

confidence: 99%

Bevel Junction Termination Extension—A New Edge Termination Technique for 4H-SiC High-Voltage Devices

Sung

Huang

Baliga

2015

IEEE Electron Device Lett.

View full text Add to dashboard Cite

A new edge termination method, referred to as a bevel junction termination extension (Bevel-JTE), is presented for high-voltage silicon carbide devices. The 4H-SiC PiN rectifiers, with a breakdown voltage of 1600 V (∼95% of the theoretical value), were fabricated using Bevel-JTEs. The Bevel-JTE technique significantly reduces the chip size by decreasing space occupied by edge termination while providing broad process latitude for parameter variations, such as implantation dose and activation anneal condition.

show abstract

Simulation and experimental study of 3-step junction termination extension for high-voltage 4H-SiC gate turn-off thyristors

Cited by 19 publications

References 15 publications

Simulation and analysis of the current–voltage–temperature characteristics of Al/Ti/4H-SiC Schottky barrier diodes

Simulation and analysis of the current–voltage–temperature characteristics of Al/Ti/4H-SiC Schottky barrier diodes

Implantation-free edge termination structures in vertical GaN power diodes

Bevel Junction Termination Extension—A New Edge Termination Technique for 4H-SiC High-Voltage Devices

Contact Info

Product

Resources

About