Simplified quantitative stress-induced leakage current (SILC) model for MOS devices

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

“…When the gate bias is applied, the application of a gate bias will immediately produce a discontinuity in current density at the interface between the two layers, causing charge accumulation there until, in steady-state, the same current density flows through the both layers. If the gate bias is removed, a discontinuity in current density will again be produced, this time causing the charge to rush out of the gate stack [28,29].…”

Modelling of stress-induced leakage current in short-channel n-MOSFETs

“…1 for drain voltages V D ¼ 0.5, 0.7 and 0.9 V with X ch the distance from the source to the drain. Since SILC increases by increasing the oxide field [5] and since the oxide field is larger in the source side than the drain side, J SILC is also larger in the source side than in the drain side as confirmed experimentally [8]. As V D increases, the difference (V G -V D ) decreases causing the oxide field to decrease.…”

“…The main idea of the model is the introduction of the concept of the equivalent oxide thickness T ox-eq over which the spatial Gaussian distribution of traps in the oxide is replaced by its maximum value N peak and the total tunnelling probability is replaced by its maximum value P max ¼ P t (x o ). The resulting formula for the SILC current density J SILC (E ox ) is given by [5]:…”

“…Stressedindexed leakage current (SILC), which is the extra current flowing through the gate oxide of MOS devices after an electrical stress, is an important reliability concern [3,4] and is usually neglected in most commercially available simulators. In a previous paper [5], we presented a simplified quantitative model for SILC in MOS devices by assuming a two-step inelastic trap-assisted tunnelling (ITAT) process as the conduction mechanism [6]. The model has the advantages of a reduced time of numerical calculations of SILC to 17% of the standard method while maintaining high accuracy of the results.…”

Stress‐induced leakage current in CNT‐MOSFETs using simplified quantitative model

“…Introduction: Stress-induced leakage current (SILC) is the extra current flowing through the gate oxide of MOS-devices after an electrical stress [1,2]. In a previous paper [3] we presented a simplified quantitative model for SILC in MOS-devices by assuming a two-step inelastic trap-assisted tunnelling (ITAT) process as the conduction mechanism [4]. The model has the advantages of a reduced time of numerical calculations of SILC to 17% of the standard method while maintaining high accuracy of the results.…”