SimLatte: A Framework to Support Testing for Worst-Case Interrupt Latencies in Embedded Software

Yu, Tingting; Srisa-an, Witawas; Cohen, Myra B.; Rothermel, Gregg

doi:10.1109/icst.2014.44

Cited by 9 publications

(8 citation statements)

References 29 publications

(45 reference statements)

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“…The number of events N to be issued is generated in terms of the specified event density. Our previous work [56] also showed that appropriately adjusting interrupt density can enhance testing effectiveness. Based on our empirical observations for the object programs (Section 4), SIMEXPLORER chooses the interrupt density to be 60%; ie, the system spends 60% of its instruction cycles executing interrupt handlers.…”

Section: Variables and Measuresmentioning

confidence: 99%

An automated framework to support testing for process‐level race conditions

Srisa-an

Rothermel

2017

Software Testing Verif & Rel

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Summary Race conditions are difficult to detect because they usually occur only under specific execution interleavings. Numerous program analysis and testing techniques have been proposed to detect race conditions between threads on single applications. However, most of these techniques neglect races that occur at the process level due to complex system event interactions. This article presents a framework, SIMEXPLORER, that allows engineers to effectively test for process‐level race conditions. SIMEXPLORER first uses dynamic analysis techniques to observe system execution, identify program locations of interest, and report faults related to oracles. Next, it uses virtualization to achieve the fine‐grained controllability needed to exercise event interleavings that are likely to expose races. We evaluated the effectiveness of SIMEXPLORER on 24 real‐world applications containing both known and unknown process‐level race conditions. Our results show that SIMEXPLORER is effective at detecting these race conditions, while incurring an overhead that is acceptable given its effectiveness improvements.

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Section: Variables and Measuresmentioning

confidence: 99%

An automated framework to support testing for process‐level race conditions

Srisa-an

Rothermel

2017

Software Testing Verif & Rel

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“…Automated test generation using search based testing techniques are described by [14] for testing worst case interrupt latencies in embedded systems. Further surveys in [15] confirms its application being extended to other non functional system attributes like safety [16], usability, quality of service [17] and security [18].…”

Section: Related Workmentioning

confidence: 99%

A Search Based Approach for Stress-Testing Integrated Circuits

Eljuse

Walkinshaw

2016

Search Based Software Engineering

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Abstract. In order to reduce software complexity and be power efficient, hardware platforms are increasingly incorporating functionality that was traditionally administered at a software-level (such as cache management). This functionality is often complex, incorporating multiple processors along with a multitude of design parameters. Such devices can only be reliably tested at a 'system' level, which presents various testing challenges; behaviour is often non-deterministic (from a software perspective), and finding suitable test sets to 'stress' the system adequately is often an inefficient, manual activity that yields fixed test sets that can rarely be reused. In this paper we investigate this problem with respect to ARM's Cache Coherency Interconnect (CCI) Unit. We present an automated search-based testing approach that combines a parameterised test-generation framework with the hill-climbing heuristic to find test sets that maximally 'stress' the CCI by producing much larger numbers of data stall cycles than the corresponding manual test sets.

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“…This article draws on two previously published conference papers , in which we proposed initial algorithms to detect WCILs and WCSUs. We have extended that work substantially by considering WCETs.…”

Section: Introductionmentioning

confidence: 99%

“…We have extended that work substantially by considering WCETs. We have also extended our work on WCILs to use a hybrid algorithm, whereas in Yu et al , we used only a GA. Finally, we have performed a larger empirical study on a more substantial base of artefacts and have generalized our approach into a framework resulting in a number of changes to both the presentation of the article along with detailed descriptions of the algorithm, evaluation, and related work.…”

Section: Introductionmentioning

confidence: 99%

A hybrid approach to testing for nonfunctional faults in embedded systems using genetic algorithms

Srisa-an

Cohen

et al. 2018

Software Testing Verif & Rel

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Embedded systems are challenging to program correctly, because they use an interrupt-driven programming paradigm and run in resource-constrained environments. This leads to various classes of nonfunctional faults that can be detected only by customized verification techniques.These nonfunctional faults are specifically related to usage of resources such as time and memory. For example, the presence of interrupts can induce delays in interrupt servicing and in system execution time. Such delays can occur when multiple interrupt service routines and interrupts of different priorities compete for resources on a given CPU. As another example, stack overflows are caused when the combination of active methods and interrupt invocations on the stack grows too large, and these can lead to data loss and other significant device failures. To detect these types of nonfunctional faults, developers need to estimate worst-case resource usage. Most existing approaches for calculating such estimates are based on static analysis; however, these have a tendency to overapproximate the resources needed. Dynamic techniques such as random testing, in contrast, often underapproximate resource usage. In this article, we present SIMESPRESSO, a framework that uses a combination of static analysis and a test case generation algorithm to estimate worst-case resource usage. There are three different worst-case resource usage scenarios that we consider: (1) worst-case execution times,(2) worst-case interrupt latencies, and (3) worst-case stack usage. SIMESPRESSO first uses static analysis to identify program paths and interrupt interleavings that potentially lead to worst-case scenarios. It then uses a genetic algorithm to generate test cases that guide program execution down these paths, using these particular interrupt interleavings. We performed an empirical study to evaluate the effectiveness of SIMESPRESSO; our results show that SIMESPRESSO is more effective than static analysis approaches and improves significantly over the state of the art dynamic technique, random test case generation. We also find that when we use only the genetic algorithm, omitting the static analysis, SIMESPRESSO performs almost as effectively, but takes significantly longer to complete its task.

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SimLatte: A Framework to Support Testing for Worst-Case Interrupt Latencies in Embedded Software

Cited by 9 publications

References 29 publications

An automated framework to support testing for process‐level race conditions

An automated framework to support testing for process‐level race conditions

A Search Based Approach for Stress-Testing Integrated Circuits

A hybrid approach to testing for nonfunctional faults in embedded systems using genetic algorithms

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