Siliconization of millimeter-wave to terahertz surface-plasmonic transceiver and phase-locked loops

Abstract

The future 6G network and big-data center will be generating and capturing a wealth of data that was previously unimaginable. The conventional inter-server interconnects rely on optical cables that can reach Tera-scale; however, they are not fully based on integrated circuit (IC) processes and hence cannot be scaled down for both cost and power. Full integration in the complementary metal-oxidesemiconductor (CMOS) technologies has been identified as the ultimate solution to build the low-cost, low-power, highly compact interconnect that meets the stringent requirement of next generation 100/400 GbE communication. Unfortunately, silicon channels suffer from strong electromagnetic crosstalk (and loss) at high speed with limited output power generated by the signal source. To overcome such issues, conventional data interfaces have implemented crosstalk-compensated equalizers and signal source leading to an excessively high 5-20 pJ/bit power efficiency. Furthermore, crosstalk-compensated equalizers have limited speeds up to 13 Gb/s.Recently, the integrated surface plasmonic polaritons (SPPs) components and circuits were proposed and implemented in silicon at the ultra-broadband terahertz (THz) frequency toward high-speed, lowpower, low-crosstalk signaling. The surface plasma (or surface wave) is a special electromagnetic (EM) wave to localize the free electron into the metal/medium interface, achieving extraordinary field confinement and enhancement. Implemented in advanced CMOS technologies, the design will be smaller, lighter, cheaper, and scalable for emerging applications such as low-crosstalk digital signaling, ultrahigh-speed communication, low-power transceiver, remote sensing, and threat detection.As there is a lack of knowledge on how to achieve surface plasmonic generation, transmission, modulation, conversion, and amplification in silicon, this thesis aims to conceptualize, design, implement, and validate several on-chip high-performance metadevices. Several I/O interface architectures are reviewed in Chapter 2, followed by the introduction of SPPs fundamentals, design, and comparison to conventional on-chip transmission lines. The impact of channel crosstalk on bit-error rate (BER) as well as power consumption will be evaluated based on link budget analysis. To evaluate how plasmonic can attenuate the channel crosstalk, the surface wave transmission lines (T-line) are modeled on the T-section network incorporated by the lossy T-line model. This model can also describe the impedance, phase shift, dispersion behavior, and loss of the surface plasmonic T-line from the circuit's perspective. Like other surface plasmonic T-lines implemented on the printed circuit boards (PCBs), impedance or momentum mismatch occurs between the TEM devices and the plasmonic devices. A gradient groove plasmonic converter is designed and experimentally verified in Chapter 3. Since the coplanar waveguide (CPW) is not involved for impedance conversion, the design is compact and therefore suitable for on-chip implementation.A split-...

Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

“…As one of metadevices for THz oscillation, the plasmonic TL and its physical properties have been discussed in detail in Liang. 45 Called plasmonic resonator, the design is featured by periodically decorating comb-shape grooves onto the metallic surface of the compact split-ring resonator. The result is that the magnetic resonance is manipulated by the SRR plasma, while the plasmonic TL couples the field from the SRR synchronizes adjacent oscillator unit-cell in the same manner.…”

“…A compact plasmonic resonator that integrates the advantages of both plasmonic TL 38–41 and split‐ring resonators 42 has been proposed in 2022, 37 aiming to improve the quality‐factor of a coupler in the CON design. As one of metadevices for THz oscillation, the plasmonic TL and its physical properties have been discussed in detail in Liang 45 . Called plasmonic resonator, the design is featured by periodically decorating comb‐shape grooves onto the metallic surface of the compact split‐ring resonator.…”

“…Such a progress benefits from the result of continuous endeavor on a broad range of research areas including 2D semiconductor materials, 13,14 photonic and solid-state devices, [15][16][17][18] heterogeneous integration, [19][20][21][22] and THz packaging. [23][24][25][26] Many pioneering works have systematically demonstrated compact THz technologies like microbolometers, [27][28][29] nanowires, [30][31][32] quantum-cascade lasers, [33][34][35] plasmonic metadevices, [36][37][38][39][40] silicon metamaterials, [41][42][43][44][45] and on-chip high-speed functional materials. [46][47][48] More importantly, many of these endeavors have paved new ways to explore techniques that can be fabricated by solid-state semiconductor technologies (silicon based or III-V semiconductors).…”